DE102004027882A1 - Multiportspeicherbaustein mit gestapelten Bänken - Google Patents

Multiportspeicherbaustein mit gestapelten Bänken Download PDF

Info

Publication number
DE102004027882A1
DE102004027882A1 DE102004027882A DE102004027882A DE102004027882A1 DE 102004027882 A1 DE102004027882 A1 DE 102004027882A1 DE 102004027882 A DE102004027882 A DE 102004027882A DE 102004027882 A DE102004027882 A DE 102004027882A DE 102004027882 A1 DE102004027882 A1 DE 102004027882A1
Authority
DE
Germany
Prior art keywords
data
buffers
write
data line
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE102004027882A
Other languages
German (de)
English (en)
Inventor
Seung-hoon Suwon Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102004027882A1 publication Critical patent/DE102004027882A1/de
Ceased legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Memory System (AREA)
DE102004027882A 2003-06-03 2004-05-28 Multiportspeicherbaustein mit gestapelten Bänken Ceased DE102004027882A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030035606A KR100546331B1 (ko) 2003-06-03 2003-06-03 스택 뱅크들 마다 독립적으로 동작하는 멀티 포트 메모리장치
KR2003-35606 2003-06-03

Publications (1)

Publication Number Publication Date
DE102004027882A1 true DE102004027882A1 (de) 2005-01-13

Family

ID=33487851

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102004027882A Ceased DE102004027882A1 (de) 2003-06-03 2004-05-28 Multiportspeicherbaustein mit gestapelten Bänken

Country Status (5)

Country Link
US (1) US7120081B2 (https=)
JP (1) JP2004362760A (https=)
KR (1) KR100546331B1 (https=)
DE (1) DE102004027882A1 (https=)
TW (1) TWI256647B (https=)

Families Citing this family (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100611404B1 (ko) * 2004-07-27 2006-08-11 주식회사 하이닉스반도체 메인 증폭기 및 반도체 장치
US7209405B2 (en) * 2005-02-23 2007-04-24 Micron Technology, Inc. Memory device and method having multiple internal data buses and memory bank interleaving
KR100670707B1 (ko) 2005-03-31 2007-01-17 주식회사 하이닉스반도체 멀티-포트 메모리 소자
US8429319B2 (en) 2005-09-28 2013-04-23 Hynix Semiconductor Inc. Multi-port memory device with serial input/output interface
KR100815176B1 (ko) * 2005-09-28 2008-03-19 주식회사 하이닉스반도체 멀티포트 메모리 장치
DE102006045248A1 (de) * 2005-09-29 2007-04-19 Hynix Semiconductor Inc., Ichon Multiport-Speichervorrichtung mit serieller Eingabe-/Ausgabeschnittstelle
KR100721581B1 (ko) 2005-09-29 2007-05-23 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자
EP1932158A4 (en) 2005-09-30 2008-10-15 Mosaid Technologies Inc MEMORY WITH OUTPUT CONTROL
US7652922B2 (en) * 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US11948629B2 (en) 2005-09-30 2024-04-02 Mosaid Technologies Incorporated Non-volatile memory device with concurrent bank operations
KR100735612B1 (ko) * 2005-12-22 2007-07-04 삼성전자주식회사 멀티패쓰 억세스블 반도체 메모리 장치
US20070150667A1 (en) * 2005-12-23 2007-06-28 Intel Corporation Multiported memory with ports mapped to bank sets
JP2007200512A (ja) * 2006-01-30 2007-08-09 Renesas Technology Corp 半導体記憶装置
KR100695436B1 (ko) * 2006-04-13 2007-03-16 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자 및그의 동작 모드 제어방법
KR100781129B1 (ko) * 2006-06-05 2007-11-30 엠텍비젼 주식회사 다중 포트 메모리 장치 및 그 데이터의 출력 방법
KR100790446B1 (ko) 2006-06-30 2008-01-02 주식회사 하이닉스반도체 스택뱅크 구조를 갖는 반도체 메모리 장치
KR100846386B1 (ko) * 2006-09-21 2008-07-15 주식회사 하이닉스반도체 멀티포트 메모리 장치
KR100837811B1 (ko) 2006-11-15 2008-06-13 주식회사 하이닉스반도체 데이터 변환 회로 및 이를 이용한 반도체 메모리 장치
KR100871083B1 (ko) * 2007-02-27 2008-11-28 삼성전자주식회사 입출력 센스앰프를 구비하는 반도체 메모리 장치의레이아웃 구조
US7817491B2 (en) 2007-09-28 2010-10-19 Hynix Semiconductor Inc. Bank control device and semiconductor device including the same
KR100990140B1 (ko) * 2007-09-28 2010-10-29 주식회사 하이닉스반도체 반도체 메모리 소자
US9123395B2 (en) * 2007-11-09 2015-09-01 SK Hynix Inc. Stack bank type semiconductor memory apparatus capable of improving alignment margin
US8181003B2 (en) * 2008-05-29 2012-05-15 Axis Semiconductor, Inc. Instruction set design, control and communication in programmable microprocessor cores and the like
JP2011146094A (ja) * 2010-01-14 2011-07-28 Renesas Electronics Corp 半導体集積回路
WO2011161798A1 (ja) * 2010-06-24 2011-12-29 富士通株式会社 半導体記憶装置及び半導体記憶装置の制御方法
US8611175B2 (en) * 2011-12-07 2013-12-17 Xilinx, Inc. Contention-free memory arrangement
CN102880569B (zh) * 2012-09-19 2015-12-16 重庆望江工业有限公司 多智能单元控制系统及其控制方法
US12537057B2 (en) 2015-09-30 2026-01-27 Sunrise Memory Corporation Three-dimensional vertical nor flash thin film transistor strings
US9842651B2 (en) 2015-11-25 2017-12-12 Sunrise Memory Corporation Three-dimensional vertical NOR flash thin film transistor strings
US11120884B2 (en) 2015-09-30 2021-09-14 Sunrise Memory Corporation Implementing logic function and generating analog signals using NOR memory strings
US9892800B2 (en) 2015-09-30 2018-02-13 Sunrise Memory Corporation Multi-gate NOR flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates
US10121553B2 (en) 2015-09-30 2018-11-06 Sunrise Memory Corporation Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays
US10608008B2 (en) 2017-06-20 2020-03-31 Sunrise Memory Corporation 3-dimensional nor strings with segmented shared source regions
US10692874B2 (en) 2017-06-20 2020-06-23 Sunrise Memory Corporation 3-dimensional NOR string arrays in segmented stacks
US10608011B2 (en) 2017-06-20 2020-03-31 Sunrise Memory Corporation 3-dimensional NOR memory array architecture and methods for fabrication thereof
US11180861B2 (en) 2017-06-20 2021-11-23 Sunrise Memory Corporation 3-dimensional NOR string arrays in segmented stacks
US10896916B2 (en) 2017-11-17 2021-01-19 Sunrise Memory Corporation Reverse memory cell
WO2019133534A1 (en) 2017-12-28 2019-07-04 Sunrise Memory Corporation 3-dimensional nor memory array with very fine pitch: device and method
US10475812B2 (en) 2018-02-02 2019-11-12 Sunrise Memory Corporation Three-dimensional vertical NOR flash thin-film transistor strings
US11069696B2 (en) 2018-07-12 2021-07-20 Sunrise Memory Corporation Device structure for a 3-dimensional NOR memory array and methods for improved erase operations applied thereto
US11751391B2 (en) 2018-07-12 2023-09-05 Sunrise Memory Corporation Methods for fabricating a 3-dimensional memory structure of nor memory strings
WO2020014655A1 (en) 2018-07-12 2020-01-16 Sunrise Memory Corporation Fabrication method for a 3-dimensional nor memory array
TWI713195B (zh) 2018-09-24 2020-12-11 美商森恩萊斯記憶體公司 三維nor記憶電路製程中之晶圓接合及其形成之積體電路
US11282855B2 (en) 2018-12-07 2022-03-22 Sunrise Memory Corporation Methods for forming multi-layer vertical NOR-type memory string arrays
JP7425069B2 (ja) 2019-01-30 2024-01-30 サンライズ メモリー コーポレイション 基板接合を用いた高帯域幅・大容量メモリ組み込み型電子デバイス
JP7655853B2 (ja) 2019-02-11 2025-04-02 サンライズ メモリー コーポレイション 垂直型薄膜トランジスタ、及び、垂直型薄膜トランジスタの、3次元メモリアレイのためのビット線コネクタとしての応用メモリ回路方法
JP2020166346A (ja) * 2019-03-28 2020-10-08 ラピスセミコンダクタ株式会社 半導体記憶装置
CN114026676B (zh) 2019-07-09 2023-05-26 日升存储公司 水平反或型存储器串的三维阵列制程
US11917821B2 (en) 2019-07-09 2024-02-27 Sunrise Memory Corporation Process for a 3-dimensional array of horizontal nor-type memory strings
KR102728539B1 (ko) 2019-10-10 2024-11-12 에스케이하이닉스 주식회사 메모리
US11515309B2 (en) 2019-12-19 2022-11-29 Sunrise Memory Corporation Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array
TWI767512B (zh) 2020-01-22 2022-06-11 美商森恩萊斯記憶體公司 薄膜儲存電晶體中冷電子抹除
US12550382B2 (en) 2020-01-22 2026-02-10 Sunrise Memory Corporation Thin-film storage transistor with ferroelectric storage layer
WO2021159028A1 (en) 2020-02-07 2021-08-12 Sunrise Memory Corporation High capacity memory circuit with low effective latency
TWI783369B (zh) 2020-02-07 2022-11-11 美商森恩萊斯記憶體公司 準揮發性系統級記憶體
US11507301B2 (en) 2020-02-24 2022-11-22 Sunrise Memory Corporation Memory module implementing memory centric architecture
WO2021173209A1 (en) 2020-02-24 2021-09-02 Sunrise Memory Corporation High capacity memory module including wafer-section memory circuit
US11561911B2 (en) 2020-02-24 2023-01-24 Sunrise Memory Corporation Channel controller for shared memory access
US11705496B2 (en) 2020-04-08 2023-07-18 Sunrise Memory Corporation Charge-trapping layer with optimized number of charge-trapping sites for fast program and erase of a memory cell in a 3-dimensional NOR memory string array
TW202220191A (zh) 2020-07-21 2022-05-16 美商日升存儲公司 用於製造nor記憶體串之3維記憶體結構之方法
US11937424B2 (en) 2020-08-31 2024-03-19 Sunrise Memory Corporation Thin-film storage transistors in a 3-dimensional array of nor memory strings and process for fabricating the same
US11842777B2 (en) 2020-11-17 2023-12-12 Sunrise Memory Corporation Methods for reducing disturb errors by refreshing data alongside programming or erase operations
US11848056B2 (en) 2020-12-08 2023-12-19 Sunrise Memory Corporation Quasi-volatile memory with enhanced sense amplifier operation
WO2022140084A1 (en) 2020-12-21 2022-06-30 Sunrise Memory Corporation Bit line and source line connections for a 3-dimensional array of memory circuits
CN116547796A (zh) 2021-01-20 2023-08-04 日升存储公司 垂直nor闪存薄膜晶体管串及其制造
WO2023287908A1 (en) 2021-07-16 2023-01-19 Sunrise Memory Corporation 3-dimensional memory string array of thin-film ferroelectric transistors
US12402319B2 (en) 2021-09-14 2025-08-26 Sunrise Memory Corporation Three-dimensional memory string array of thin-film ferroelectric transistors formed with an oxide semiconductor channel
CN117373508A (zh) * 2022-06-30 2024-01-09 深圳市中兴微电子技术有限公司 多端口存储器、多端口存储器的读写方法及装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63269393A (ja) * 1987-04-28 1988-11-07 Matsushita Electric Ind Co Ltd 多ポ−ト半導体記憶素子
JP2500740B2 (ja) * 1993-04-06 1996-05-29 日本電気株式会社 デュアルポ―トメモリ
JP3523004B2 (ja) * 1997-03-19 2004-04-26 株式会社東芝 同期式ランダムアクセスメモリ
JP4000233B2 (ja) * 1998-06-03 2007-10-31 富士通株式会社 半導体記憶装置及びデータバス制御方法
JP2000182370A (ja) * 1998-12-16 2000-06-30 Toshiba Corp 半導体記憶装置
JP2000215659A (ja) * 1999-01-27 2000-08-04 Fujitsu Ltd 半導体メモリ及び情報処理装置
KR100326086B1 (ko) * 2000-02-03 2002-03-07 윤종용 반도체 메모리 장치 및 이 장치의 프리차지 방법
JP3940539B2 (ja) * 2000-02-03 2007-07-04 株式会社日立製作所 半導体集積回路
JP2002109884A (ja) * 2000-09-27 2002-04-12 Toshiba Corp メモリ装置
DE10054520C1 (de) * 2000-11-03 2002-03-21 Infineon Technologies Ag Datenspeicher mit mehreren Bänken
US6603683B2 (en) * 2001-06-25 2003-08-05 International Business Machines Corporation Decoding scheme for a stacked bank architecture
US6940753B2 (en) * 2002-09-24 2005-09-06 Sandisk Corporation Highly compact non-volatile memory and method therefor with space-efficient data registers
US7571287B2 (en) * 2003-03-13 2009-08-04 Marvell World Trade Ltd. Multiport memory architecture, devices and systems including the same, and methods of using the same
KR100532433B1 (ko) * 2003-05-07 2005-11-30 삼성전자주식회사 하나의 패드를 통하여 데이터를 동시에 입출력하기 위한장치 및 방법
US7006402B2 (en) * 2003-08-29 2006-02-28 Hynix Semiconductor Inc Multi-port memory device

Also Published As

Publication number Publication date
KR100546331B1 (ko) 2006-01-26
US7120081B2 (en) 2006-10-10
JP2004362760A (ja) 2004-12-24
TW200519963A (en) 2005-06-16
US20040246807A1 (en) 2004-12-09
TWI256647B (en) 2006-06-11
KR20040105007A (ko) 2004-12-14

Similar Documents

Publication Publication Date Title
DE102004027882A1 (de) Multiportspeicherbaustein mit gestapelten Bänken
DE69535672T2 (de) Synchrone NAND DRAM Architektur
DE69810132T2 (de) Multiport drams mit internen cache-speichern
DE4308665B4 (de) DRAM mit einer bidirektionalen globalen Bitleitung
DE3928902C2 (de) Halbleiterspeicher und Verfahren zum Betreiben desselben und Verwendung desselben in einem Video-RAM
DE19961138C2 (de) Multiport-RAM-Speichervorrichtung
DE10309919B4 (de) Pufferbaustein und Speichermodule
DE69429289T2 (de) Synchroner dynamischer Direktzugriffspeicher
DE3788747T2 (de) Halbleiterspeicher.
DE3783666T2 (de) Halbleiterspeicheranordnung.
DE3906895C2 (https=)
DE69224447T2 (de) Direktzugriffspeicher und sein Steuerverfahren in Pipe-Line-Seitenmodus
DE202007018730U1 (de) Inegrierte Schaltung mit abgestuftem Abschluss auf dem Chip
DE4036091A1 (de) Halbleiterspeicheranordnung mit einem in eine anzahl von zellenbloecken unterteilten zellenarray
DE19748502A1 (de) Halbleiterspeichereinrichtung, auf die mit hoher Geschwindigkeit zugegriffen werden kann
DE112007003069T5 (de) Mit Hochgeschwindigkeit arbeitende, aufgefächerte Systemarchitektur und Eingabe/Ausgabe-Schaltungen für nicht flüchtigen Speicher
DE4022149A1 (de) Halbleiterspeichereinrichtung und betriebsverfahren fuer diese
EP1105877B1 (de) Speichersystem
DE19756929B4 (de) Zellenarray und Leseverstärkerstruktur mit verbesserten Rauscheigenschaften und verringerter Größe
DE102006062399A1 (de) Halbleiterspeicherbauelement mit mehreren Speicherbereichen, Zugriffsverfahren und Testverfahren
DE102012107577A1 (de) Multiport-Speicherelement sowie Halbleitervorrichtung und System mit demselben
DE112006003503T5 (de) Mehrfachanschluss-Speicher mit Banksätzen zugeordneten Anschlüssen
DE102004022355B4 (de) Halbleiterbaustein mit bidirektionalem Eingabe-/Ausgabeanschluss und zugehöriges Verfahren zum Ein- und Ausgeben von Daten
DE10058227A1 (de) Halbleiterspeicherbauelement, Durchlass-/Zwischenspeichereinheit hierfür und zugehöriges Datenübertragungsverfahren
DE2121490A1 (de) Orthogonaler Datenspeicher

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection