KR100384761B1 - Ｎ２ｏ 질화 산화물 트렌치 측벽과 절연구조를 형성하는 방법 - Google Patents

Ｎ２ｏ 질화 산화물 트렌치 측벽과 절연구조를 형성하는 방법 Download PDF

Info

Publication number
KR100384761B1
KR100384761B1 KR10-1999-7005969A KR19997005969A KR100384761B1 KR 100384761 B1 KR100384761 B1 KR 100384761B1 KR 19997005969 A KR19997005969 A KR 19997005969A KR 100384761 B1 KR100384761 B1 KR 100384761B1
Authority
KR
South Korea
Prior art keywords
oxide layer
trench
nitride
oxygen
oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-1999-7005969A
Other languages
English (en)
Korean (ko)
Other versions
KR20000069813A (ko
Inventor
아르가바니레자
차우로버트에스.
양사이몬
그라함존
Original Assignee
인텔 코오퍼레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인텔 코오퍼레이션 filed Critical 인텔 코오퍼레이션
Publication of KR20000069813A publication Critical patent/KR20000069813A/ko
Application granted granted Critical
Publication of KR100384761B1 publication Critical patent/KR100384761B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
KR10-1999-7005969A 1996-12-31 1997-12-16 Ｎ２ｏ 질화 산화물 트렌치 측벽과 절연구조를 형성하는 방법 Expired - Fee Related KR100384761B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US8/775,571 1996-12-31
US08/775,571 US5780346A (en) 1996-12-31 1996-12-31 N2 O nitrided-oxide trench sidewalls and method of making isolation structure
US08/775,571 1996-12-31

Publications (2)

Publication Number Publication Date
KR20000069813A KR20000069813A (ko) 2000-11-25
KR100384761B1 true KR100384761B1 (ko) 2003-05-22

Family

ID=25104813

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-1999-7005969A Expired - Fee Related KR100384761B1 (ko) 1996-12-31 1997-12-16 Ｎ２ｏ 질화 산화물 트렌치 측벽과 절연구조를 형성하는 방법

Country Status (8)

Country Link
US (3) US5780346A (enExample)
EP (1) EP1002336B1 (enExample)
JP (1) JP4518573B2 (enExample)
KR (1) KR100384761B1 (enExample)
AU (1) AU5705798A (enExample)
DE (1) DE69733842T2 (enExample)
IL (1) IL130562A (enExample)
WO (1) WO1998029905A1 (enExample)

Families Citing this family (101)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5985735A (en) * 1995-09-29 1999-11-16 Intel Corporation Trench isolation process using nitrogen preconditioning to reduce crystal defects
US6114741A (en) * 1996-12-13 2000-09-05 Texas Instruments Incorporated Trench isolation of a CMOS structure
US5780346A (en) * 1996-12-31 1998-07-14 Intel Corporation N2 O nitrided-oxide trench sidewalls and method of making isolation structure
US5763315A (en) * 1997-01-28 1998-06-09 International Business Machines Corporation Shallow trench isolation with oxide-nitride/oxynitride liner
JPH10214888A (ja) * 1997-01-30 1998-08-11 Nec Yamagata Ltd 半導体装置の製造方法
US6096662A (en) * 1997-03-26 2000-08-01 Advanced Micro Devices, Inc. NH3 /N2 plasma treatment to enhance the adhesion of silicon nitride to thermal oxide
US6399462B1 (en) * 1997-06-30 2002-06-04 Cypress Semiconductor Corporation Method and structure for isolating integrated circuit components and/or semiconductor active devices
JPH11111710A (ja) * 1997-10-01 1999-04-23 Nec Corp 半導体装置およびその製造方法
TW501230B (en) * 1997-10-04 2002-09-01 United Microelectronics Corp Manufacture method shallow trench isolation
US6284633B1 (en) * 1997-11-24 2001-09-04 Motorola Inc. Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode
US6051478A (en) * 1997-12-18 2000-04-18 Advanced Micro Devices, Inc. Method of enhancing trench edge oxide quality
US6080682A (en) * 1997-12-18 2000-06-27 Advanced Micro Devices, Inc. Methodology for achieving dual gate oxide thicknesses
JPH11204788A (ja) * 1998-01-19 1999-07-30 Toshiba Corp 半導体装置およびその製造方法
KR100280106B1 (ko) * 1998-04-16 2001-03-02 윤종용 트렌치 격리 형성 방법
US5989977A (en) * 1998-04-20 1999-11-23 Texas Instruments - Acer Incorporated Shallow trench isolation process
US6727569B1 (en) * 1998-04-21 2004-04-27 Advanced Micro Devices, Inc. Method of making enhanced trench oxide with low temperature nitrogen integration
US6153480A (en) * 1998-05-08 2000-11-28 Intel Coroporation Advanced trench sidewall oxide for shallow trench technology
KR100289340B1 (ko) * 1998-06-12 2001-06-01 윤종용 트렌치격리제조방법
US6248429B1 (en) * 1998-07-06 2001-06-19 Micron Technology, Inc. Metallized recess in a substrate
US6156620A (en) * 1998-07-22 2000-12-05 Lsi Logic Corporation Isolation trench in semiconductor substrate with nitrogen-containing barrier region, and process for forming same
US6355540B2 (en) * 1998-07-27 2002-03-12 Acer Semicondutor Manufacturing Inc. Stress-free shallow trench isolation
JP4592837B2 (ja) * 1998-07-31 2010-12-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6245638B1 (en) * 1998-08-03 2001-06-12 Advanced Micro Devices Trench and gate dielectric formation for semiconductor devices
US6265282B1 (en) 1998-08-17 2001-07-24 Micron Technology, Inc. Process for making an isolation structure
US6274498B1 (en) * 1998-09-03 2001-08-14 Micron Technology, Inc. Methods of forming materials within openings, and method of forming isolation regions
US6372601B1 (en) * 1998-09-03 2002-04-16 Micron Technology, Inc. Isolation region forming methods
KR100292616B1 (ko) * 1998-10-09 2001-07-12 윤종용 트렌치격리의제조방법
JP2000133700A (ja) * 1998-10-22 2000-05-12 Mitsubishi Electric Corp 半導体装置およびその製造方法
TW396521B (en) * 1998-11-06 2000-07-01 United Microelectronics Corp Process for shallow trench isolation
US7157314B2 (en) 1998-11-16 2007-01-02 Sandisk Corporation Vertically stacked field programmable nonvolatile memory and method of fabrication
US6200880B1 (en) * 1998-11-16 2001-03-13 United Microelectronics Corp. Method for forming shallow trench isolation
US6245635B1 (en) * 1998-11-30 2001-06-12 United Microelectronics Corp. Method of fabricating shallow trench isolation
US6080637A (en) * 1998-12-07 2000-06-27 Taiwan Semiconductor Manufacturing Company Shallow trench isolation technology to eliminate a kink effect
JP3955404B2 (ja) * 1998-12-28 2007-08-08 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
KR100470160B1 (ko) * 1998-12-30 2005-04-06 주식회사 하이닉스반도체 반도체 소자의 소자분리막 형성 방법
US6037238A (en) * 1999-01-04 2000-03-14 Vanguard International Semiconductor Corporation Process to reduce defect formation occurring during shallow trench isolation formation
KR100322531B1 (ko) * 1999-01-11 2002-03-18 윤종용 파임방지막을 이용하는 반도체소자의 트랜치 소자분리방법 및이를 이용한 반도체소자
US6027982A (en) * 1999-02-05 2000-02-22 Chartered Semiconductor Manufacturing Ltd. Method to form shallow trench isolation structures with improved isolation fill and surface planarity
JP2000260867A (ja) * 1999-03-09 2000-09-22 Toshiba Corp 半導体装置および半導体装置の製造方法
US6180489B1 (en) * 1999-04-12 2001-01-30 Vanguard International Semiconductor Corporation Formation of finely controlled shallow trench isolation for ULSI process
KR100319620B1 (ko) * 1999-05-10 2002-01-05 김영환 반도체 소자의 격리구조 및 그 제조방법
JP2000323563A (ja) * 1999-05-14 2000-11-24 Nec Corp 半導体装置の製造方法
US6255194B1 (en) * 1999-06-03 2001-07-03 Samsung Electronics Co., Ltd. Trench isolation method
JP4649006B2 (ja) * 1999-07-16 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置
US6200881B1 (en) * 1999-07-23 2001-03-13 Worldwide Semiconductor Manufacturing Corp. Method of forming a shallow trench isolation
US6323106B1 (en) * 1999-09-02 2001-11-27 Lsi Logic Corporation Dual nitrogen implantation techniques for oxynitride formation in semiconductor devices
JP2001085511A (ja) * 1999-09-14 2001-03-30 Toshiba Corp 素子分離方法
KR100338767B1 (ko) 1999-10-12 2002-05-30 윤종용 트렌치 소자분리 구조와 이를 갖는 반도체 소자 및 트렌치 소자분리 방법
US6313011B1 (en) * 1999-10-28 2001-11-06 Koninklijke Philips Electronics N.V. (Kpenv) Method for suppressing narrow width effects in CMOS technology
JP2001144170A (ja) 1999-11-11 2001-05-25 Mitsubishi Electric Corp 半導体装置およびその製造方法
EP1104936A1 (en) * 1999-11-25 2001-06-06 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device, and semiconductor device manufactured thereby
US6174787B1 (en) * 1999-12-30 2001-01-16 White Oak Semiconductor Partnership Silicon corner rounding by ion implantation for shallow trench isolation
US6495449B1 (en) * 2000-03-07 2002-12-17 Simplus Systems Corporation Multilayered diffusion barrier structure for improving adhesion property
US6670266B2 (en) * 2000-03-07 2003-12-30 Simplus Systems Corporation Multilayered diffusion barrier structure for improving adhesion property
US6368931B1 (en) 2000-03-27 2002-04-09 Intel Corporation Thin tensile layers in shallow trench isolation and method of making same
US8575719B2 (en) 2000-04-28 2013-11-05 Sandisk 3D Llc Silicon nitride antifuse for use in diode-antifuse memory arrays
US6313007B1 (en) 2000-06-07 2001-11-06 Agere Systems Guardian Corp. Semiconductor device, trench isolation structure and methods of formations
KR20020002161A (ko) * 2000-06-29 2002-01-09 박종섭 반도체 소자분리막 형성방법
KR100339890B1 (ko) * 2000-08-02 2002-06-10 윤종용 자기정렬된 셸로우 트렌치 소자분리 방법 및 이를 이용한불휘발성 메모리 장치의 제조방법
US6417070B1 (en) 2000-12-13 2002-07-09 International Business Machines Corporation Method for forming a liner in a trench
US6432797B1 (en) * 2001-01-25 2002-08-13 Chartered Semiconductor Manufacturing Ltd. Simplified method to reduce or eliminate STI oxide divots
DE10104037A1 (de) * 2001-01-31 2002-08-22 Elmos Semiconductor Ag Substrat für integrierte Halbleiterkomponenten
US6335259B1 (en) * 2001-02-22 2002-01-01 Macronix International Co., Ltd. Method of forming shallow trench isolation
US7267037B2 (en) 2001-05-05 2007-09-11 David Walter Smith Bidirectional singulation saw and method
DE10222083B4 (de) * 2001-05-18 2010-09-23 Samsung Electronics Co., Ltd., Suwon Isolationsverfahren für eine Halbleitervorrichtung
JP5121102B2 (ja) * 2001-07-11 2013-01-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR100428768B1 (ko) * 2001-08-29 2004-04-30 삼성전자주식회사 트렌치 소자 분리형 반도체 장치 및 그 형성 방법
US6777307B1 (en) * 2001-12-04 2004-08-17 Cypress Semiconductor Corp. Method of forming semiconductor structures with reduced step heights
DE10162065A1 (de) * 2001-12-17 2003-06-26 Infineon Technologies Ag Verfahren zum Grabenätzen
US20040108573A1 (en) * 2002-03-13 2004-06-10 Matrix Semiconductor, Inc. Use in semiconductor devices of dielectric antifuses grown on silicide
US20030194871A1 (en) * 2002-04-15 2003-10-16 Macronix International Co., Ltd. Method of stress and damage elimination during formation of isolation device
TWI252565B (en) * 2002-06-24 2006-04-01 Hitachi Ltd Semiconductor device and manufacturing method thereof
KR100486757B1 (ko) * 2002-07-15 2005-05-03 매그나칩 반도체 유한회사 소자 격리 특성을 향상시킨 이미지센서 및 그 제조 방법
WO2004023549A1 (ja) * 2002-08-30 2004-03-18 Fujitsu Amd Semiconductor Limited 半導体装置及びその製造方法
US6784075B2 (en) 2002-09-10 2004-08-31 Silicon Integrated Systems Corp. Method of forming shallow trench isolation with silicon oxynitride barrier film
US6727160B1 (en) * 2002-10-15 2004-04-27 Silicon Integrated Systems Corp. Method of forming a shallow trench isolation structure
KR100497603B1 (ko) * 2003-03-17 2005-07-01 삼성전자주식회사 트렌치 소자 분리 방법 및 이를 이용한 불휘발성 메모리장치의 제조방법
US6887798B2 (en) * 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US7996825B2 (en) * 2003-10-31 2011-08-09 Hewlett-Packard Development Company, L.P. Cross-file inlining by using summaries and global worklist
JP2005277196A (ja) * 2004-03-25 2005-10-06 Elpida Memory Inc 半導体装置の製造方法
JP2006024895A (ja) * 2004-06-07 2006-01-26 Renesas Technology Corp 半導体装置およびその製造方法
US20060003546A1 (en) * 2004-06-30 2006-01-05 Andreas Klipp Gap-filling for isolation
KR100607330B1 (ko) * 2004-10-25 2006-07-28 에스티마이크로일렉트로닉스 엔.브이. 반도체 소자의 소자 분리막 형성 방법
JP2007035823A (ja) * 2005-07-26 2007-02-08 Elpida Memory Inc トレンチ形成方法、半導体装置の製造方法および半導体装置
KR100731102B1 (ko) * 2005-12-29 2007-06-22 동부일렉트로닉스 주식회사 이미지 센서 및 이의 제조방법
KR100678645B1 (ko) * 2006-01-13 2007-02-06 삼성전자주식회사 반도체 소자 및 그 제조 방법
US7635655B2 (en) * 2006-03-30 2009-12-22 Tokyo Electron Limited Method for replacing a nitrous oxide based oxidation process with a nitric oxide based oxidation process for substrate processing
KR100854870B1 (ko) * 2006-05-12 2008-08-28 주식회사 하이닉스반도체 반도체 소자의 제조방법
JP4446202B2 (ja) * 2006-09-22 2010-04-07 エルピーダメモリ株式会社 半導体装置及び半導体装置の製造方法
KR100829600B1 (ko) 2006-10-02 2008-05-14 삼성전자주식회사 비휘발성 메모리 장치의 제조 방법
KR100845102B1 (ko) * 2006-12-20 2008-07-09 동부일렉트로닉스 주식회사 반도체 소자의 소자분리막 형성방법
KR100842749B1 (ko) * 2007-03-27 2008-07-01 주식회사 하이닉스반도체 반도체소자의 트렌치 소자분리막 형성방법
JP2009283494A (ja) * 2008-05-19 2009-12-03 Seiko Epson Corp 半導体装置の製造方法
US8043933B2 (en) * 2008-11-24 2011-10-25 Applied Materials, Inc. Integration sequences with top surface profile modification
JP5549410B2 (ja) * 2010-06-18 2014-07-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8921183B2 (en) * 2010-12-08 2014-12-30 Nanya Technology Corporation Method for fabricating trench isolation structure
FR2972564B1 (fr) * 2011-03-08 2016-11-04 S O I Tec Silicon On Insulator Tech Procédé de traitement d'une structure de type semi-conducteur sur isolant
CN103295950B (zh) * 2012-02-27 2015-05-20 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构的制作方法
US8829642B2 (en) * 2012-03-29 2014-09-09 The Institute of Microelectronics, Chinese Academy of Science Semiconductor device and method for manufacturing the same
KR102317646B1 (ko) * 2015-04-14 2021-10-27 삼성전자주식회사 반도체 소자 및 이의 제조 방법
CN114400203A (zh) * 2022-01-24 2022-04-26 长鑫存储技术有限公司 一种半导体结构及其制备方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960015920A (ko) * 1994-10-06 1996-05-22 윌리엄 티. 엘리스 절연체상 실리콘(soi) 트렌치 구조물 및 이의 제조 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3883889A (en) * 1974-04-15 1975-05-13 Micro Power Systems Inc Silicon-oxygen-nitrogen layers for semiconductor devices
US3976524A (en) * 1974-06-17 1976-08-24 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
US4621414A (en) * 1985-03-04 1986-11-11 Advanced Micro Devices, Inc. Method of making an isolation slot for integrated circuit structure
US4960727A (en) * 1987-11-17 1990-10-02 Motorola, Inc. Method for forming a dielectric filled trench
US4871689A (en) * 1987-11-17 1989-10-03 Motorola Inc. Multilayer trench isolation process and structure
US5004703A (en) * 1989-07-21 1991-04-02 Motorola Multiple trench semiconductor structure method
JP2932552B2 (ja) * 1989-12-29 1999-08-09 日本電気株式会社 半導体装置及びその製造方法
US5387540A (en) * 1993-09-30 1995-02-07 Motorola Inc. Method of forming trench isolation structure in an integrated circuit
JPH08203884A (ja) 1995-01-31 1996-08-09 Mitsubishi Electric Corp オキシナイトライド膜およびその形成方法ならびにそのオキシナイトライド膜を用いた素子分離酸化膜の形成方法
US5719085A (en) * 1995-09-29 1998-02-17 Intel Corporation Shallow trench isolation technique
US5985735A (en) * 1995-09-29 1999-11-16 Intel Corporation Trench isolation process using nitrogen preconditioning to reduce crystal defects
US5780346A (en) * 1996-12-31 1998-07-14 Intel Corporation N2 O nitrided-oxide trench sidewalls and method of making isolation structure
JP4145359B2 (ja) * 1997-04-07 2008-09-03 エヌエックスピー ビー ヴィ 半導体装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960015920A (ko) * 1994-10-06 1996-05-22 윌리엄 티. 엘리스 절연체상 실리콘(soi) 트렌치 구조물 및 이의 제조 방법

Also Published As

Publication number Publication date
US5780346A (en) 1998-07-14
IL130562A (en) 2003-12-10
EP1002336A1 (en) 2000-05-24
JP4518573B2 (ja) 2010-08-04
WO1998029905A1 (en) 1998-07-09
IL130562A0 (en) 2000-06-01
EP1002336B1 (en) 2005-07-27
AU5705798A (en) 1998-07-31
US6261925B1 (en) 2001-07-17
DE69733842T2 (de) 2006-04-27
KR20000069813A (ko) 2000-11-25
US6566727B1 (en) 2003-05-20
EP1002336A4 (en) 2000-05-24
JP2001507864A (ja) 2001-06-12
DE69733842D1 (de) 2005-09-01

Similar Documents

Publication Publication Date Title
KR100384761B1 (ko) Ｎ２ｏ 질화 산화물 트렌치 측벽과 절연구조를 형성하는 방법
US6153480A (en) Advanced trench sidewall oxide for shallow trench technology
US6297126B1 (en) Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts
US5930644A (en) Method of forming a shallow trench isolation using oxide slope etching
KR20010063781A (ko) 반도체소자의 제조방법
KR0157875B1 (ko) 반도체 장치의 제조방법
KR100243302B1 (ko) 반도체장치의 트렌치 소자분리 방법
US5679601A (en) LOCOS method using encapsulating polysilicon/silicon nitride spacer
US6013559A (en) Method of forming trench isolation
US6245638B1 (en) Trench and gate dielectric formation for semiconductor devices
US5970364A (en) Method of nitride-sealed oxide-buffered local oxidation of silicon
US20030181014A1 (en) Method of manufacturing semiconductor device with STI
KR100271400B1 (ko) 트랜치구조를이용한반도체소자의절연막형성방법
KR100242385B1 (ko) 반도체장치의 소자격리방법
KR100492790B1 (ko) 반도체소자의소자분리절연막형성방법
KR100571486B1 (ko) 반도체 소자의 제조 방법
KR940006090B1 (ko) 반도체 소자 격리 방법
KR20030001941A (ko) 반도체소자의 제조방법
JPH11297814A (ja) 半導体装置およびその製造方法
KR20010025923A (ko) 얕은 트렌치 소자분리 방법
KR100814257B1 (ko) 반도체 소자 제조 방법
KR100473728B1 (ko) 반도체 소자의 소자 분리막 형성 방법
KR100388458B1 (ko) 트렌치 소자분리 공정을 사용하는 반도체 소자 제조방법
KR100469761B1 (ko) 소자분리막 형성 방법
KR20000027850A (ko) 반도체소자의 소자분리막형성방법

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20130503

Year of fee payment: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

FPAY Annual fee payment

Payment date: 20140502

Year of fee payment: 12

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20150430

Year of fee payment: 13

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 13

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20160510

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20160510