JP2001507864A - ホウ素の外部拡散を防ぎ応力を減少させるためのn▲下2▼o窒化酸化物トレンチ側壁 - Google Patents
ホウ素の外部拡散を防ぎ応力を減少させるためのn▲下2▼o窒化酸化物トレンチ側壁Info
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- JP2001507864A JP2001507864A JP53009198A JP53009198A JP2001507864A JP 2001507864 A JP2001507864 A JP 2001507864A JP 53009198 A JP53009198 A JP 53009198A JP 53009198 A JP53009198 A JP 53009198A JP 2001507864 A JP2001507864 A JP 2001507864A
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- oxide layer
- trench
- oxide
- semiconductor substrate
- isolation structure
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- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 title description 8
- 229910052796 boron Inorganic materials 0.000 title description 8
- 238000000034 method Methods 0.000 claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 238000002955 isolation Methods 0.000 claims abstract description 57
- 239000004065 semiconductor Substances 0.000 claims abstract description 53
- 239000007789 gas Substances 0.000 claims abstract description 11
- 238000005498 polishing Methods 0.000 claims description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052710 silicon Inorganic materials 0.000 claims description 31
- 239000010703 silicon Substances 0.000 claims description 31
- 150000004767 nitrides Chemical class 0.000 claims description 21
- 238000005229 chemical vapour deposition Methods 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 15
- 238000004140 cleaning Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 12
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims 3
- 230000000779 depleting effect Effects 0.000 claims 1
- 239000002019 doping agent Substances 0.000 abstract description 30
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 abstract description 18
- 238000000137 annealing Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 16
- 239000010409 thin film Substances 0.000 description 15
- 239000000463 material Substances 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 10
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 9
- 229910052757 nitrogen Inorganic materials 0.000 description 8
- 230000005684 electric field Effects 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 230000005672 electromagnetic field Effects 0.000 description 5
- 238000000926 separation method Methods 0.000 description 5
- 238000005121 nitriding Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- SDTHIDMOBRXVOQ-UHFFFAOYSA-N 5-[bis(2-chloroethyl)amino]-6-methyl-1h-pyrimidine-2,4-dione Chemical compound CC=1NC(=O)NC(=O)C=1N(CCCl)CCCl SDTHIDMOBRXVOQ-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 241000894007 species Species 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
- H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.半導体基板に分離構造を形成する方法であって、 a)前記半導体基板にトレンチをエッチングする段階と、 b)前記トレンチ内の第1の酸化物層を形成する段階と、 c)前記第1の酸化物層を酸化窒素(N2O)基体雰囲気にさらして、前記第1 の酸化物層上にオキシ窒化物面を形成し、前記第1の酸化物層と前記半導体基板 との間にシリコン・オキシ窒化物界面を形成する段階と、 d)前記第1の酸化物層の前記オキシ窒化物面上に、第2の酸化物層を堆積させ る段階と を含む方法。 2.前記トレンチをエッチングする前記段階の後でかつ前記第1の酸化物層を 形成する前記段階の前に、トレンチのプレクリーニングを実行する段階をさらに 含む請求項1項に記載の方法。 3.化学機械的研磨(CMP)エッチバック段階を実行して、前記トレンチ内 の前記第1と第2の酸化物層を分離する段階をさらに含む請求項1項に記載の方 法。 4.前記第1の酸化物層が、前記トレンチ内に熱酸化物を成長させる段階を含 む方法によって形成される請求項1項に記載の方法。 5.前記第2の酸化物層が、化学気相成長(CVD)プロセスによって堆積さ れる請求項1項に記載の方法。 6.半導体基板内に分離構造を形成する方法であって、 a)前記半導体基板にトレンチをエッチングする段階と、 b)前記トレンチ内に熱酸化物を成長させて、第1の酸化物層を形成する段階と 、c)前記第1の酸化物層を酸化窒素(N2O)ガス雰囲気にさらして、前記第 1の酸化物層上にオキシ窒化物面を形成し、前記第1の酸化物層と前記半導体基 板の間にシリコン・オキシ窒化物界面を形成し、前記N2O基体雰囲気処理段階 が、前記半導体基板の一部を消耗し、前記トレンチの上角部を丸くする段階と、 d)前記第1の酸化物層の前記オキシ窒化物面上に第2の酸化物層を堆積させる 段階と、 e)化学機械的研磨エッチバック段階を実行して、前記トレンチ内の前記第1と 第2の酸化物層を分離する段階と を含む方法。 7.前記第2の酸化物層が、実質上、ドープされていない酸化物層である請求 項6項に記載の方法。 8.前記第2の酸化物層が、BSG、PSG、BPSGおよびそれらの任意の 組合せからなるグループから選択されたドープされた酸化物である請求項6項に 記載の方法。 9.前記第2の酸化物層が、化学気相成長法(CVD)プロセスによって堆積 された請求項6項に記載の方法。 10.CVDプロセスが、TEOSを使用して行われた減圧CVDプロセスで ある請求項9項に記載の方法。 11.半導体基板内に分離構造を形成する方法であって、 a)前記半導体基板上にパッド酸化物層を形成する段階と、 b)前記パッド酸化物層上に研磨ストップ層を形成する段階と、 c)前記研磨ストップ層と前記パッド酸化物層をパターニングしてエッチングす る段階と、 d)前記半導体基板内にトレンチをエッチングする段階と、 e)トレンチのプレクリーニング段階を実行する段階と、 f)前記トレンチ内に第1の酸化物層を形成して、第1のトレンチ酸化物層を形 成する段階と、 g)前記第1の酸化物層を酸化窒素(N2O)ガス雰囲気にさらして、前記第1 の酸化物層上にオキシ窒化物面を形成し、前記第1の酸化物層と前記半導体基板 の間にシリコン・オキシ窒化物界面を形成し、前記N2O基体雰囲気処理段階が 、前記半導体基板の一部を消耗し、前記トレンチの上角部を丸くする段階と、 h)前記第1のトレンチ酸化物層の前記オキシ窒化物面上に、第2のトレンチ酸 化物層を堆積させる段階と、 i)前記第2のトレンチ酸化物層を研磨して、前記第2のトレンチ酸化物層の前 記研磨ストップ層の上の部分を除去する段階と、 j)前記研磨ストップ層を除去する段階と、 k)化学機械的研磨エッチバック段階を実行して、前記トレンチ内の前記第1と 第2の酸化物層を分離する段階と、 1)半導体素子の形成に使用するために、前記半導体基板と前記トレンチの上に 薄いゲート酸化物層を形成する段階と、 を含む方法。 12.前記半導体基板が、シリコンを含む請求項11項に記載の方法。 13.前記研磨ストップ層が、窒化物層を含む請求項11項に記載の方法。 14.前記トレンチのプレクリーニング段階が、SC1、SC2およびHFを 含む化学作用を利用して行われる請求項11項に記載の方法。 15.前記第1のトレンチ酸化物層が熱酸化物を含む請求項11項に記載の方 法。 16.前記N2Oガス雰囲気処理段階が、前記シリコンの一部を消耗して、シ リコン・オキシ窒化物面を形成し、前記トレンチの上角部を丸くする請求項12 項に記載の方法。 17.前記第2の酸化物層が、化学気相成長(CVD)プロセスによって堆積 される請求項11項に記載の方法。 18.前記第2のトレンチ酸化物層が、実質上ドープされていない酸化物層で ある請求項11項に記載の方法。 19.前記第2の酸化物層が、BSG、PSG、BPSGおよびそれらの任意 の組合せからなるグループから選択されたドープされた酸化物である請求項11 項に記載の方法。 20.前記薄いゲート酸化物層が、32Å未満の厚さを有する請求項11項に 記載の方法。 21.半導体基板に形成された分離構造であって、 前記半導体基板内のトレンチと、 前記トレンチの内面に形成され、オキシ窒化物面を有する第1の酸化物層と、 前記第1の酸化物層と前記半導体基板の間のシリコン・オキシ窒化物界面と、 前記トレンチ内の、前記第1の酸化物層の前記オキシ窒化物面上に直接配置さ れた第2の酸化物層と を含む分離構造。 22.前記トレンチが、浅いトレンチ分離構造である請求項21項に記載の分 離構造。 23.前記第1の酸化物層が、熱酸化物である請求項21項に記載の分離構造 。 24.前記第2の酸化物層が、実質上ドープされていない酸化物である請求項 21項に記載の分離構造。 25.前記第2の酸化物層が、BSG、PSG、BPSGおよびそれらの任意 の組合せからなるグループから選択されたドープされた酸化物である請求項21 項に記載の方法。 26.半導体基板内に形成された分離構造であって、 前記半導体基板内のトレンチと、 前記トレンチの内側に形成され、オキシ窒化物面を有する第1の酸化物層と、 前記第1の酸化物層と前記半導体基板の間のシリコン・オキシ窒化物界面と、 前記トレンチ内に、前記第1の酸化物層の前記オキシ窒化物面上に直配置され た第2の酸化物層とを有する分離構造と、 前記分離構造の隣りにあり、32Å未満の厚さを有する薄いゲート酸化物層を 含むトランジスタと を含む半導体素子。 27.前記トレンチが、浅いトレンチ分離構造である請求項26項に記載の分 離構造。 28.前記第1の酸化物層が、熱酸化物である請求項26項に記載の分離構造 。 29.前記第2の酸化物層が、実質上ドープされていない酸化物である請求項 項26項に記載の分離構造。 30.前記第2の酸化物層が、BSG、PSG、BPSGおよびそれらの任意 の組合せからなるグループから選択されたドープされた酸化物である請求項26 項に記載の分離構造。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/775,571 US5780346A (en) | 1996-12-31 | 1996-12-31 | N2 O nitrided-oxide trench sidewalls and method of making isolation structure |
US08/775,571 | 1996-12-31 | ||
PCT/US1997/023307 WO1998029905A1 (en) | 1996-12-31 | 1997-12-16 | N2o nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2001507864A true JP2001507864A (ja) | 2001-06-12 |
JP2001507864A5 JP2001507864A5 (ja) | 2005-06-16 |
JP4518573B2 JP4518573B2 (ja) | 2010-08-04 |
Family
ID=25104813
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP53009198A Expired - Fee Related JP4518573B2 (ja) | 1996-12-31 | 1997-12-16 | ホウ素の外部拡散を防ぎ応力を減少させるためのn▲下2▼o窒化酸化物トレンチ側壁 |
Country Status (8)
Country | Link |
---|---|
US (3) | US5780346A (ja) |
EP (1) | EP1002336B1 (ja) |
JP (1) | JP4518573B2 (ja) |
KR (1) | KR100384761B1 (ja) |
AU (1) | AU5705798A (ja) |
DE (1) | DE69733842T2 (ja) |
IL (1) | IL130562A (ja) |
WO (1) | WO1998029905A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003031796A (ja) * | 2001-07-11 | 2003-01-31 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2006024895A (ja) * | 2004-06-07 | 2006-01-26 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2009283494A (ja) * | 2008-05-19 | 2009-12-03 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2010232677A (ja) * | 2010-06-18 | 2010-10-14 | Renesas Electronics Corp | 半導体装置の製造方法 |
Families Citing this family (96)
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US5985735A (en) * | 1995-09-29 | 1999-11-16 | Intel Corporation | Trench isolation process using nitrogen preconditioning to reduce crystal defects |
US6114741A (en) * | 1996-12-13 | 2000-09-05 | Texas Instruments Incorporated | Trench isolation of a CMOS structure |
US5780346A (en) * | 1996-12-31 | 1998-07-14 | Intel Corporation | N2 O nitrided-oxide trench sidewalls and method of making isolation structure |
US5763315A (en) * | 1997-01-28 | 1998-06-09 | International Business Machines Corporation | Shallow trench isolation with oxide-nitride/oxynitride liner |
JPH10214888A (ja) * | 1997-01-30 | 1998-08-11 | Nec Yamagata Ltd | 半導体装置の製造方法 |
US6096662A (en) * | 1997-03-26 | 2000-08-01 | Advanced Micro Devices, Inc. | NH3 /N2 plasma treatment to enhance the adhesion of silicon nitride to thermal oxide |
US6399462B1 (en) * | 1997-06-30 | 2002-06-04 | Cypress Semiconductor Corporation | Method and structure for isolating integrated circuit components and/or semiconductor active devices |
JPH11111710A (ja) * | 1997-10-01 | 1999-04-23 | Nec Corp | 半導体装置およびその製造方法 |
TW501230B (en) * | 1997-10-04 | 2002-09-01 | United Microelectronics Corp | Manufacture method shallow trench isolation |
US6284633B1 (en) * | 1997-11-24 | 2001-09-04 | Motorola Inc. | Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode |
US6080682A (en) * | 1997-12-18 | 2000-06-27 | Advanced Micro Devices, Inc. | Methodology for achieving dual gate oxide thicknesses |
US6051478A (en) * | 1997-12-18 | 2000-04-18 | Advanced Micro Devices, Inc. | Method of enhancing trench edge oxide quality |
JPH11204788A (ja) * | 1998-01-19 | 1999-07-30 | Toshiba Corp | 半導体装置およびその製造方法 |
KR100280106B1 (ko) * | 1998-04-16 | 2001-03-02 | 윤종용 | 트렌치 격리 형성 방법 |
US5989977A (en) * | 1998-04-20 | 1999-11-23 | Texas Instruments - Acer Incorporated | Shallow trench isolation process |
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- 1997-12-16 EP EP97953276A patent/EP1002336B1/en not_active Expired - Lifetime
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- 1997-12-16 AU AU57057/98A patent/AU5705798A/en not_active Abandoned
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Cited By (4)
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JP2003031796A (ja) * | 2001-07-11 | 2003-01-31 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2006024895A (ja) * | 2004-06-07 | 2006-01-26 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2009283494A (ja) * | 2008-05-19 | 2009-12-03 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2010232677A (ja) * | 2010-06-18 | 2010-10-14 | Renesas Electronics Corp | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
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IL130562A (en) | 2003-12-10 |
AU5705798A (en) | 1998-07-31 |
US5780346A (en) | 1998-07-14 |
WO1998029905A1 (en) | 1998-07-09 |
DE69733842D1 (de) | 2005-09-01 |
EP1002336A1 (en) | 2000-05-24 |
IL130562A0 (en) | 2000-06-01 |
US6261925B1 (en) | 2001-07-17 |
KR100384761B1 (ko) | 2003-05-22 |
US6566727B1 (en) | 2003-05-20 |
KR20000069813A (ko) | 2000-11-25 |
EP1002336B1 (en) | 2005-07-27 |
DE69733842T2 (de) | 2006-04-27 |
EP1002336A4 (en) | 2000-05-24 |
JP4518573B2 (ja) | 2010-08-04 |
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