US5679601A - LOCOS method using encapsulating polysilicon/silicon nitride spacer - Google Patents
LOCOS method using encapsulating polysilicon/silicon nitride spacer Download PDFInfo
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- US5679601A US5679601A US08/763,282 US76328296A US5679601A US 5679601 A US5679601 A US 5679601A US 76328296 A US76328296 A US 76328296A US 5679601 A US5679601 A US 5679601A
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- silicon nitride
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- oxide layer
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- 229910052581 Si3N4 Inorganic materials 0.000 title claims abstract description 73
- 238000000034 method Methods 0.000 title claims abstract description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000002955 isolation Methods 0.000 claims abstract description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims 2
- 238000001039 wet etching Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 20
- 229910052710 silicon Inorganic materials 0.000 abstract description 20
- 239000010703 silicon Substances 0.000 abstract description 20
- 230000003647 oxidation Effects 0.000 abstract description 14
- 238000007254 oxidation reaction Methods 0.000 abstract description 14
- 241000293849 Cordylanthus Species 0.000 description 11
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 9
- 230000007547 defect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- 229910017900 NH4 F Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
Definitions
- the present invention relates to a method of forming isolation regions, and more particularly to an improved local oxidation of silicon (LOCOS) method via the use of encapsulating polysilicon/silicon nitride spacer.
- LOC local oxidation of silicon
- MOS metal-oxide-semiconductor
- bipolar integrated circuit technology as many as hundreds of thousands of devices are used in a single chip. Improper isolation among transistors will cause current leakage, which can consume significant power for the entire chip. In addition, improper isolation can further escalate latchup to damage the circuit function momentarily or permanently. Still further, improper isolation can result in noise margin degradation, voltage shift or crosstalk.
- isolation is usually practiced by forming the isolation regions between neighboring active regions.
- an isolation region is formed by ion-doping a channel stop layer of polarity opposite to the source electrode and the drain electrode of the integrated circuit device, and growing a thick oxide, often referred to as field oxide (FOX).
- FOX field oxide
- the channel stop and the FOX cause the threshold voltage in the isolation region to be much higher than those of the neighboring active devices, making surface inversion not occur under the field oxide region.
- LOCOS Local oxidation of silicon
- silicon nitride layer is used as an efficient oxidation mask which prevents the oxidants from reaching the silicon surface covered by silicon nitride.
- the silicon nitride layer oxidizes very slowly compared to silicon.
- direct deposition of silicon nitride on silicon can cause stress-induced defects when the structure is subjected to oxidation at elevated temperature. These defects can be considerably reduced by forming a thin (100 ⁇ 500 angstroms) pad oxide layer between silicon and silicon nitride.
- the pad oxide reduces the force transmitted to silicon by relieving the stress. It acts as a buffer which cushions the transition of stress between silicon and silicon nitride.
- the pad oxide layer provides a lateral path for oxidation of silicon.
- This lateral extension of oxidation through pad oxide is frequently called bird's beak because of its form.
- the extent of the bird's beak can be reduced by decreasing the thickness of the pad oxide, which, however will cause more stress-induced defects from the above silicon nitride layer. Therefore, the thickness of the pad oxide and the silicon nitride layer must be optimized to minimize the extent of the bird's beak without generating defects.
- the sealed-interface local oxidation (SILO) process uses an additional thin silicon nitride film over the silicon substrate followed by forming an oxide layer and a thick silicon nitride layer.
- the SILO can reduce the bird's beak, but at the expense of generating more stress, more crystal defects, and higher leakage currents. See pp.554-561, of J. Hui, et al., "Sealed-interface local oxidation technology," IEEE Trans. Electron Devices, vol. ED-29, 1982.
- BOX buried oxide
- Beside bird's beak effect another important limitation is the sharp decrease in the field oxide thickness as the isolation spacing is reduced below 1 micrometer. As the width of the isolation region decreases, the resultant field oxide becomes thinner. This effect is frequency called field oxide thinning effect, and is more serious for deep submicron semiconductor devices. See p.671, of A. Bryant, et al., "Characteristics of CMOS device isolation for the ULSI age,” IEDM, 1994.
- a method for forming a field oxide region that substantially suppresses the bird's beak effect and the oxidation stress, and improves the field oxide thinning effect.
- a pad oxide layer having a thickness of 200 ⁇ 1000 angstroms, is grown at about 800°-1100° C. in a conventional furnace.
- a silicon nitride layer with a thickness of 500-3000 angstroms is deposited, for example, using low pressure chemical vapor deposition (LPCVD) process.
- LPCVD low pressure chemical vapor deposition
- the silicon nitride layer and the pad oxide are removed anisotropically using the photoresist pattern as a mask, via use of a dry etching process.
- a wet etchant such as diluted hydrofluoric (HF) solution is used for its advantage of dissolving silicon dioxide without attacking silicon and silicon nitride.
- HF diluted hydrofluoric
- the HF is mixed with ammonium fluoride (NH 4 F), known as buffered oxide etching (BOE), to slow down the etch rate for a controllable process.
- NH 4 F ammonium fluoride
- Another thin silicon dioxide layer having a thickness of about 0 ⁇ 300 angstroms, is grown on the silicon substrate. Then a thin polysilicon layer with a thickness of 0-300 angstroms is deposited using low pressure CVD by the decomposition of silane or ultra-high vaccum CVD (UHVCVD) at about 450° ⁇ 700° C. at a pressure of about 0.05 ⁇ 2.0 torr.
- silane or ultra-high vaccum CVD UHVCVD
- a thin (30 ⁇ 500 angstroms) silicon nitride layer is deposited using conventional chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). Thereafter, the silicon nitride layer is etched back via use of a reactive ion etch process (RIE) to form a spacer.
- LPCVD chemical vapor deposition
- PECVD plasma-enhanced chemical vapor deposition
- portions of the polysilicon layer, the silicon oxide layer and the substrate are etched using the spacer as a mask, thereby resulting in a recessed substrate.
- This etching process is preferrably performed using reactive ion etch or plasma etch.
- the recessed substrate can result in thicker field oxides beneath the silicon substrate.
- this recess of the substrate can be omitted for those semiconductor devices having isolation spacing larger than 1 micrometer.
- a field oxide having a thickness of about 3000 ⁇ 8000 angstroms is grown in a conventional furnace at about 900°-1100° C. Accordingly, a field isolation with little or no bird's beak is achieved by combining conventional LOCOS with the encapsulating polysilicon/silicon nitride spacers technology of the present invention. Further, the oxidation stress can be minimized using the encapsulating polysilicon layer as a buffer layer. After the silicon nitride layer, the polysilicon layer, the silicon nitride spacer, and the pad oxide are conventionally removed using suitable etching method, a semiconductor device such as metal-oxide-semiconductor (MOS) transistor can be fabricated between the field oxide regions.
- MOS metal-oxide-semiconductor
- FIGS. 1 to 10 illustrate schematically cross-sectional views of the structure formed at various stages in the fabrication of an isolation region in accordance with the invention.
- FIG. 1 shows a schematic cross-section of a semiconductor substrate 10.
- a silicon oxide layer 12, having a thickness of 200 ⁇ 1000 angstroms, is grown at about 800°-1000° C. in a conventional furnace.
- a silicon nitride layer 14 is deposited, for example, using low pressure chemical vapor deposition (LPCVD) process.
- the silicon nitride layer 14 has a thickness of about 500 ⁇ 3000 angstroms.
- the silicon oxide layer 12 is frequency called pad oxide in isolation technology, and is used to reduce the force transmitted from the silicon nitride layer 14 to the substrate 10.
- the silicon nitride layer 14 is, however, used as an oxidation mask which prevents the oxidants from reaching the substrate surface under the silicon nitride layer 14 in a later oxidation step. Thereafter, a photoresist masking layer 16 having active region pattern is formed over the silicon nitride layer 14. This pattern is defined using well known photoresist coating, exposure and development processes.
- FIG. 2 shows the structure alter the silicon nitride layer 14 and the pad oxide 12 are removed anisotropically using the photoresist pattern 16 as a mask, via use of a dry etching process.
- FIG. 3 shows the step of oxide undercut to etch isotropically portions of the pad oxide 12 away.
- the lateral undercut depth is between 0 and 1000 angstroms.
- a wet etchant such as diluted hydrofluoric (HF) solution is used for its advantage of dissolving silicon dioxide without attacking silicon and silicon nitride.
- HF diluted hydrofluoric
- the HF is mixed with ammonium fluoride (NH 4 F), known as buffered oxide etching (BOE), to slow down the etch rate for a controllable process.
- NH 4 F ammonium fluoride
- BOE buffered oxide etching
- another thin silicon dioxide layer 18 having a thickness of about 0 ⁇ 300 angstroms, is grown on the silicon substrate 10. Noticeably, little silicon oxide is grown on the silicon nitride 14 because the silicon nitride oxidizes very slowly compared to silicon.
- a polysilicon layer 10 having a thickness of about 30 ⁇ 300 angstroms, is deposited using low pressure CVD or ultra-high vaccum CVD (UHVCVD).
- the LPCVD process forms the polysilicon layer 20 by the decomposition of silane at about 450° ⁇ 700° C. at a pressure of about 0.05 ⁇ 2.0 torr, according to the reaction:
- a thin (30 ⁇ 500 angstroms) silicon nitride layer 22 is deposited using conventional chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) over the resultant structure of FIG. 5. Thereafter, the silicon nitride layer 22 is etched back via use of a reactive ion etch process (RIE) to form a spacer 22, as shown in FIG. 7.
- LPCVD chemical vapor deposition
- PECVD plasma-enhanced chemical vapor deposition
- Portions of the polysilicon layer 20, the silicon oxide layer 18 and the substrate 10 are etched using the silicon nitride spacer 22 as a mask, therefore resulting in a recessed substrate 10 as shown in FIG. 8.
- the silicon substrate 10 is recessed from 0 to 2000 angstroms. This etch process is preferrably performed using reactive ion etch or plasma etch. For fabricating deep sub-micron semiconductor devices, which have narrower isolation regions, the recessed substrate can result in thicker field oxides. However, this recess of the substrate 10 can be omitted for those semiconductor devices having isolation spacing larger than 1 micrometer.
- a field oxide 28 having a thickness of about 3000 ⁇ 8000 angstroms, is grown in a conventional furnace at about 900°-1100° C. as shown in FIG. 9. Accordingly, a field isolation with little or no bird's beak is achieved by combining conventional LOCOS with the encapsulating polysilicon/silicon nitride spacer technology of the present invention. Further, the oxidation stress can be minimized using the encapsulating polysilicon layer as a buffer layer.
- MOS metal-oxide-semiconductor
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
Claims (18)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/763,282 US5679601A (en) | 1996-12-10 | 1996-12-10 | LOCOS method using encapsulating polysilicon/silicon nitride spacer |
TW086112112A TW368721B (en) | 1996-12-10 | 1997-08-22 | Local oxidation method employing polycide/silicon nitride clearance wall by controlling the width of pad oxide and silicon nitride to optimize the forming of isolation area |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/763,282 US5679601A (en) | 1996-12-10 | 1996-12-10 | LOCOS method using encapsulating polysilicon/silicon nitride spacer |
Publications (1)
Publication Number | Publication Date |
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US5679601A true US5679601A (en) | 1997-10-21 |
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US08/763,282 Expired - Lifetime US5679601A (en) | 1996-12-10 | 1996-12-10 | LOCOS method using encapsulating polysilicon/silicon nitride spacer |
Country Status (2)
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US (1) | US5679601A (en) |
TW (1) | TW368721B (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5930649A (en) * | 1996-07-22 | 1999-07-27 | Lg Semicon Co., Ltd. | Method of forming device isolating layer of semiconductor device |
US5989977A (en) * | 1998-04-20 | 1999-11-23 | Texas Instruments - Acer Incorporated | Shallow trench isolation process |
US6074932A (en) * | 1998-01-28 | 2000-06-13 | Texas Instruments - Acer Incorporated | Method for forming a stress-free shallow trench isolation |
US6133118A (en) * | 1997-08-22 | 2000-10-17 | Acer Semiconductor Manufacturing Inc. | Edge polysilicon buffer LOCOS isolation |
KR20010058339A (en) * | 1999-12-27 | 2001-07-05 | 박종섭 | Method for forming isolation layer of semiconductor device |
US6344374B1 (en) * | 2000-10-12 | 2002-02-05 | Vanguard International Semiconductor Corporation | Method of fabricating insulators for isolating electronic devices |
US7071111B2 (en) * | 2001-10-25 | 2006-07-04 | Intersil Americas Inc. | Sealed nitride layer for integrated circuits |
CN1322571C (en) * | 2004-06-30 | 2007-06-20 | 北京大学 | Isolating method for silicon mesa vertical channel field effect transistor |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5175123A (en) * | 1990-11-13 | 1992-12-29 | Motorola, Inc. | High-pressure polysilicon encapsulated localized oxidation of silicon |
US5393692A (en) * | 1993-07-28 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Recessed side-wall poly plugged local oxidation |
US5563091A (en) * | 1993-12-14 | 1996-10-08 | Goldstar Electron Co., Ltd. | Method for isolating semiconductor elements |
US5612248A (en) * | 1995-10-11 | 1997-03-18 | Micron Technology, Inc. | Method for forming field oxide or other insulators during the formation of a semiconductor device |
-
1996
- 1996-12-10 US US08/763,282 patent/US5679601A/en not_active Expired - Lifetime
-
1997
- 1997-08-22 TW TW086112112A patent/TW368721B/en not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5175123A (en) * | 1990-11-13 | 1992-12-29 | Motorola, Inc. | High-pressure polysilicon encapsulated localized oxidation of silicon |
US5393692A (en) * | 1993-07-28 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Recessed side-wall poly plugged local oxidation |
US5563091A (en) * | 1993-12-14 | 1996-10-08 | Goldstar Electron Co., Ltd. | Method for isolating semiconductor elements |
US5612248A (en) * | 1995-10-11 | 1997-03-18 | Micron Technology, Inc. | Method for forming field oxide or other insulators during the formation of a semiconductor device |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5930649A (en) * | 1996-07-22 | 1999-07-27 | Lg Semicon Co., Ltd. | Method of forming device isolating layer of semiconductor device |
US6133118A (en) * | 1997-08-22 | 2000-10-17 | Acer Semiconductor Manufacturing Inc. | Edge polysilicon buffer LOCOS isolation |
US6074932A (en) * | 1998-01-28 | 2000-06-13 | Texas Instruments - Acer Incorporated | Method for forming a stress-free shallow trench isolation |
US5989977A (en) * | 1998-04-20 | 1999-11-23 | Texas Instruments - Acer Incorporated | Shallow trench isolation process |
KR20010058339A (en) * | 1999-12-27 | 2001-07-05 | 박종섭 | Method for forming isolation layer of semiconductor device |
US6344374B1 (en) * | 2000-10-12 | 2002-02-05 | Vanguard International Semiconductor Corporation | Method of fabricating insulators for isolating electronic devices |
US7071111B2 (en) * | 2001-10-25 | 2006-07-04 | Intersil Americas Inc. | Sealed nitride layer for integrated circuits |
US20060231864A1 (en) * | 2001-10-25 | 2006-10-19 | Intersil Americas Inc. | Sealed nitride layer for integrated circuits |
US7605445B2 (en) | 2001-10-25 | 2009-10-20 | Intersil Americas Inc. | Sealed nitride layer for integrated circuits |
CN1322571C (en) * | 2004-06-30 | 2007-06-20 | 北京大学 | Isolating method for silicon mesa vertical channel field effect transistor |
Also Published As
Publication number | Publication date |
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TW368721B (en) | 1999-09-01 |
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