JP6494802B2 - 電力用半導体装置および電力用半導体装置を製造する方法 - Google Patents
電力用半導体装置および電力用半導体装置を製造する方法 Download PDFInfo
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- JP6494802B2 JP6494802B2 JP2017562511A JP2017562511A JP6494802B2 JP 6494802 B2 JP6494802 B2 JP 6494802B2 JP 2017562511 A JP2017562511 A JP 2017562511A JP 2017562511 A JP2017562511 A JP 2017562511A JP 6494802 B2 JP6494802 B2 JP 6494802B2
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Description
図1Aは、本発明の実施形態1によるパワーモジュール10を示す平面図であり、図1Bは、図1AのA−A線断面図である。パワーモジュール10は、基板1と、基板1の上に焼結性金属接合材2を用いて接合された(つまり、焼結性金属接合材からなる接合層を介して設けられた)半導体素子3とを備える。
次に、実施例(サンプルS1〜S4)を用いて本発明の実施形態1を具体的に説明するが、これらは本発明を限定するものではない。まず、実施例で用いた基板1、焼結性金属接合材2および半導体素子3について説明する。
絶縁性セラミックの一例であるSi3N4の両面に、金属の一例であるCuを用いた導電層を、ろう材により貼り合わせて基板1を準備した。Si3N4の線膨張係数は約3ppm/℃であり、Cuの線膨張係数は約17ppm/℃である。従って、Cu板の厚さが大きいほど基板1全体としての線膨張係数が大きくなる。半導体素子3と焼結性金属接合材2に加わる応力および生じる歪を小さくするために、Cu板は薄いことが好ましい。具体的には、Cu板の厚さは、好ましくは1.0mm以下であり、より好ましくは0.5mm以下である。本実施例ではこの条件を満たすように、Si3N4板の厚さは0.3mm、Cu板の厚さは0.8mmとした。なお、前記基板は、厚さ0.8mmのCu層と、厚さ0.3mmのSi3N4層と、厚さ0.8mmのCu層がこの順番で積層された3層構造を有している。基板の等価線膨脹係数は12(ppm/K)であり、等価弾性率は150GPaである。
焼結性金属接合材2として焼結性銀(Ag)ペーストを用いた。焼結性銀(Ag)ペーストは、前記乾燥条件、前記マウント条件および前記接合条件の範囲内で接合した。
半導体素子3の材料にはシリコン(Si)を用いた。半導体素子3の寸法は15mm×15mm、厚さは0.15mmとした。表面メタライズ層5と裏面メタライズ層6の層構成は共に、母材側からAlSi層/Ti層/Ni層/Au層とした。表面メタライズ層5と裏面メタライズ層6は同じ層構成を有するので、両層5,6を1つの処理工程で同時に設けた。サンプルS1〜S4では表面メタライズ層5の厚さwfに対する裏面メタライズ層6の厚さwrの比(wr/wf)を下記の通り変化させた。ただし、表面メタライズ層5と裏面メタライズ層6はNi層の厚さのみが異なり、AlSi層、Ti層およびAu層の厚さ同じであってかつNi層の厚さと比べて充分に小さい。
サンプルS1:wr/wf=1.0μm/1.7μm=0.17
サンプルS2:wr/wf=1.8μm/9.0μm=0.20
サンプルS3:wr/wf=4.4μm/8.0μm=0.55
サンプルS4:wr/wf=4.6μm/7.0μm≒0.65
ヒートサイクル試験後、焼結性金属接合材2、裏面メタライズ層6にクラックは発生していない。
0.55×(αf×Ef/αr×Er)・・・(1)
上限値は下記の式(2)で計算できる。
1.8/(αf×Ef/αr×Er)・・・(2)
表面メタライズ層5または裏面メタライズ層6が複数層構造(L1,L2,L3…)を有し、各層の線膨張係数がα1,α2,α3…であり、各層の縦弾性係数がE1,E2,E3…であり、各層の厚さがt1,t2,t3…である場合、等価線膨張係数αsは下記の式(3)で計算できる。
αs={(α1×E1×t1)+(α2×E2×t2)+(α3×E3×t3)…}/{(E1×t1)+(E2×t2)+(E3×t3)+…}・・・(3)
等価縦弾性係数Esは下記の式(4)で計算できる。
Es={(E1×t1)+(E2×t2)+(E3×t3)+…)/(t1+t2+t3)+…}・・・(4)
図6は、本発明の実施形態2によるパワーモジュール20を示す、図1Bに対応する断面図である。図7は、図6の部分拡大図である。実施形態1では、半導体素子3の表面メタライズ層5と裏面メタライズ層6とがそれぞれ単層構造を有する例について説明した。本実施形態2では、表面メタライズ層25と裏面メタライズ層26とがそれぞれ複数層構造を有する例について説明すると共に、それぞれ好ましい層構成について検討する。なお、半導体素子の表面メタライズ層と裏面メタライズ層の層構成を除けば、本実施形態2のパワーモジュール20は実施形態1のパワーモジュール10と同一または対応する構成要素を有する。これらの構成要素について、説明、図面では同じ符号を付して詳しい説明を省略する。図7では、半導体素子23がIGBTである例について説明するが、本発明はこれに限定されることはない。
図8Aは、本発明の実施形態3によるパワーモジュール30を示す平面図であり、図8Bは、図8AのB−B線断面図である。図9は、図8Bの部分拡大図である。なお、半導体素子の表裏面のメタライズ層の層構成を除けば、本実施形態3のパワーモジュール30は実施形態1のパワーモジュール10と同一または対応する構成要素を有する。これらの構成要素について、説明、図面では同じ符号を付して詳しい説明を省略する。
次に、実施例を用いて本発明の実施形態3を具体的に説明するが、これは本発明を限定するものではない。図10のグラフは、横軸が、表面メタライズ層35の厚さに対する裏面メタライズ層36の厚さの比を表し、縦軸が、半導体素子33の反り量を示す。
図11は、本発明の実施形態4によるパワーモジュールに搭載される半導体素子43を示す、図9に対応する断面図である。実施形態3では、半導体素子33の表面メタライズ層35と裏面メタライズ層36がそれぞれ単層構造を有する例について説明した。本実施形態4では、表面メタライズ層45と裏面メタライズ層46(それぞれメタライズ層35,36に対応する)とがそれぞれ複数層構造を有する例について説明すると共に、それぞれ好ましい層構成について検討する。なお、半導体素子の表面メタライズ層と裏面メタライズ層の層構成を除けば、本実施形態4のパワーモジュールは実施形態3のパワーモジュール30と同一または対応する構成要素を有する。これらの構成要素について、説明、図面では同じ符号を付して詳しい説明を省略する。
図12A,12B、図13A,13Bを参照して、本発明の実施の形態5を説明する。図12A,Bに示すように、本実施形態5によるパワーモジュール50は、基板1と、基板1の上に焼結性金属接合材2を用いて接合された半導体素子53とを備える。半導体素子53は、母材54と、母材54の表面に設けられた表面メタライズ層55と、母材54の裏面に設けられた裏面メタライズ層56とを有する。
Claims (7)
- 基板を準備する工程と、
母材と、前記母材の第1面に設けられた第1導電層と、前記母材の第1面に対向する第2面に設けられた第2導電層とを有する半導体素子を準備する工程と、
前記基板の上に焼結性金属接合材を設ける工程と、
前記焼結性金属接合材の上に前記半導体素子を仮固定する仮固定工程と、
前記焼結性金属接合材を焼結させ、前記焼結性金属接合材の上に前記半導体素子を接合する接合工程とを含み、
前記第1導電層は、厚さ1.5μm以上のNi層を含み、
前記第2導電層は、前記第1導電層のNi層の厚さの0.5倍以上2.0倍以下の厚さを有するNi層を含み、
前記第1導電層と前記第2導電層とを1つの処理により形成する、電力用半導体装置を製造する方法。 - 基板を準備する工程と、
母材と、前記母材の第1面に設けられた第1導電層と、前記母材の第1面に対向する第2面に設けられた第2導電層とを有する半導体素子を準備する工程と、
前記基板の上に焼結性金属接合材を設ける工程と、
前記焼結性金属接合材の上に前記半導体素子を仮固定する仮固定工程と、
前記焼結性金属接合材を焼結させ、前記焼結性金属接合材の上に前記半導体素子を接合する接合工程とを含み、
前記第1導電層は、厚さ1.5μm以上のNi層を含み、
前記第2導電層は、前記第1導電層のNi層の厚さの0.5倍以上2.0倍以下の厚さを有するNi層を含み、
前記仮固定工程は、前記接合工程で前記半導体素子を加圧する圧力よりも小さな圧力で前記半導体素子を加圧しながら、前記半導体素子を仮固定する工程であることを特徴とする、電力用半導体装置を製造する方法。 - 基板を準備する工程と、
母材と、前記母材の第1面に設けられた第1導電層と、前記母材の第1面に対向する第2面に設けられた第2導電層とを有する半導体素子を準備する工程と、
前記基板の上に焼結性金属接合材を設ける工程と、
前記焼結性金属接合材の上に前記半導体素子を仮固定する仮固定工程と、
前記焼結性金属接合材を焼結させ、前記焼結性金属接合材の上に前記半導体素子を接合する接合工程とを含み、
前記第1導電層は、厚さ1.5μm以上のNi層を含み、
前記第2導電層は、前記第1導電層のNi層の厚さの0.5倍以上2.0倍以下の厚さを有するNi層を含み、
前記仮固定工程は、25℃以上200℃以下の温度環境下で、1分以下の時間、0.01MPa以上5MPa以下の圧力を加えて前記半導体素子を仮固定する工程であり、
前記接合工程は、250℃以上350℃以下の温度環境下で、1分以上60分以下の時間、0.1MPa以上50MPa以下の圧力を加えて前記半導体素子を接合する工程であることを特徴とする、電力用半導体装置を製造する方法。 - 前記半導体素子の第2導電層の上に配線金属板をはんだ接合する工程をさらに含む、
請求項1〜3のいずれか1項に記載の電力用半導体装置を製造する方法。 - 前記基板の母材の厚さは、150μm以下である、
請求項1〜4のいずれか1項に記載の電力用半導体装置を製造する方法。 - 前記第1導電層と前記第2導電層のうち少なくとも一方が、複数層構造を有する、
請求項1〜5のいずれか1項に記載の電力用半導体装置を製造する方法。 - 前記焼結性金属接合材の金属は、Ag、CuおよびNiから成る群から選択される、
請求項1〜6のいずれか1項に記載の電力用半導体装置を製造する方法。
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