JP6115505B2 - 電子装置 - Google Patents

電子装置 Download PDF

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Publication number
JP6115505B2
JP6115505B2 JP2014065942A JP2014065942A JP6115505B2 JP 6115505 B2 JP6115505 B2 JP 6115505B2 JP 2014065942 A JP2014065942 A JP 2014065942A JP 2014065942 A JP2014065942 A JP 2014065942A JP 6115505 B2 JP6115505 B2 JP 6115505B2
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JP
Japan
Prior art keywords
substrate
mold resin
electronic device
mold
electronic component
Prior art date
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Active
Application number
JP2014065942A
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English (en)
Japanese (ja)
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JP2015026811A (ja
JP2015026811A5 (enExample
Inventor
典久 今泉
典久 今泉
祐紀 眞田
祐紀 眞田
竹中　正幸
正幸 竹中
慎也 内堀
慎也 内堀
賢吾 岡
賢吾 岡
太助 福田
太助 福田
圭太郎 中間
圭太郎 中間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
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Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2014065942A priority Critical patent/JP6115505B2/ja
Priority to US14/894,637 priority patent/US9941182B2/en
Priority to PCT/JP2014/002924 priority patent/WO2014203477A1/ja
Publication of JP2015026811A publication Critical patent/JP2015026811A/ja
Publication of JP2015026811A5 publication Critical patent/JP2015026811A5/ja
Application granted granted Critical
Publication of JP6115505B2 publication Critical patent/JP6115505B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Geometry (AREA)
JP2014065942A 2013-06-21 2014-03-27 電子装置 Active JP6115505B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2014065942A JP6115505B2 (ja) 2013-06-21 2014-03-27 電子装置
US14/894,637 US9941182B2 (en) 2013-06-21 2014-06-03 Electronic device and method for manufacturing same
PCT/JP2014/002924 WO2014203477A1 (ja) 2013-06-21 2014-06-03 電子装置およびその製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2013130304 2013-06-21
JP2013130304 2013-06-21
JP2014065942A JP6115505B2 (ja) 2013-06-21 2014-03-27 電子装置

Publications (3)

Publication Number Publication Date
JP2015026811A JP2015026811A (ja) 2015-02-05
JP2015026811A5 JP2015026811A5 (enExample) 2015-10-15
JP6115505B2 true JP6115505B2 (ja) 2017-04-19

Family

ID=52104229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014065942A Active JP6115505B2 (ja) 2013-06-21 2014-03-27 電子装置

Country Status (3)

Country Link
US (1) US9941182B2 (enExample)
JP (1) JP6115505B2 (enExample)
WO (1) WO2014203477A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6194804B2 (ja) 2014-01-23 2017-09-13 株式会社デンソー モールドパッケージ
WO2018202615A1 (en) * 2017-05-02 2018-11-08 Abb Schweiz Ag Resin encapsulated power semiconductor module with exposed terminal areas
KR102825809B1 (ko) * 2020-07-10 2025-06-27 삼성전자주식회사 언더필이 구비된 반도체 패키지 및 이의 제조 방법

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01175240A (ja) 1987-12-28 1989-07-11 Sharp Corp 半導体チップの製造方法
US5834336A (en) * 1996-03-12 1998-11-10 Texas Instruments Incorporated Backside encapsulation of tape automated bonding device
JP3569386B2 (ja) 1996-05-27 2004-09-22 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法およびそれにより得られるモジュール基板ならびに電子機器
DE19640304C2 (de) * 1996-09-30 2000-10-12 Siemens Ag Chipmodul insbesondere zur Implantation in einen Chipkartenkörper
JP3859318B2 (ja) 1997-08-29 2006-12-20 シチズン電子株式会社 電子回路のパッケージ方法
JP2000040711A (ja) 1998-07-23 2000-02-08 Sony Corp 樹脂封止型半導体装置とその製造方法
JP2002110718A (ja) 2000-09-29 2002-04-12 Hitachi Ltd 半導体装置の製造方法
JP2002190565A (ja) 2000-12-20 2002-07-05 Taiyo Yuden Co Ltd ハイブリッドｉｃ及びその製造方法
JP3820991B2 (ja) * 2002-01-08 2006-09-13 日立電線株式会社 半導体装置及びその製造方法
JP2005161695A (ja) * 2003-12-03 2005-06-23 Towa Corp 樹脂封止装置及び樹脂封止方法
JP4477976B2 (ja) * 2004-09-30 2010-06-09 株式会社ルネサステクノロジ 半導体装置の製造方法
WO2006129926A1 (en) 2005-06-02 2006-12-07 Tsp Co., Ltd. Mold for manufacturing semiconductor device and semiconductor device manufactred using the same
JP2007109831A (ja) 2005-10-13 2007-04-26 Towa Corp 電子部品の樹脂封止成形方法
FR2893764B1 (fr) * 2005-11-21 2008-06-13 St Microelectronics Sa Boitier semi-conducteur empilable et procede pour sa fabrication
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JP5419230B2 (ja) * 2011-08-01 2014-02-19 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
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Also Published As

Publication number Publication date
US9941182B2 (en) 2018-04-10
JP2015026811A (ja) 2015-02-05
US20160104653A1 (en) 2016-04-14
WO2014203477A1 (ja) 2014-12-24

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