CN102931105A - 半导体器件管芯键合 - Google Patents

半导体器件管芯键合 Download PDF

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Publication number
CN102931105A
CN102931105A CN2011102277551A CN201110227755A CN102931105A CN 102931105 A CN102931105 A CN 102931105A CN 2011102277551 A CN2011102277551 A CN 2011102277551A CN 201110227755 A CN201110227755 A CN 201110227755A CN 102931105 A CN102931105 A CN 102931105A
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China
Prior art keywords
semiconductor element
tube core
electric contacts
undercutting
die attach
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CN2011102277551A
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邱书楠
贡国良
骆军华
徐雪松
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NXP USA Inc
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Freescale Semiconductor Inc
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Priority to CN2011102277551A priority Critical patent/CN102931105A/zh
Priority to US13/495,011 priority patent/US20130037966A1/en
Publication of CN102931105A publication Critical patent/CN102931105A/zh
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Abstract

本发明公开了一种半导体器件,该半导体器件包括具有相反的第一面和第二面以及边缘表面的半导体管芯。边缘表面具有在第一面之下的底切。半导体管芯的第二面以管芯附接材料键合至管芯支撑部件(例如,引线框的导热旗座)的键合表面。键合材料的填角形成于底切之内。

Description

半导体器件管芯键合
技术领域
本发明涉及半导体管芯封装的方法,并且更特别地,涉及控制用于将半导体管芯附接于管芯支撑部件的材料的填角高度的方法
背景技术
半导体器件封装实现了基本功能,例如,提供到/来自半导体管芯的外部电连接以及保护管芯免受机械的和环境的应力。在封装管芯的常见方法中,晶片被切单并且切单的管芯被键合于管芯支撑件,例如衬底或者引线框的管芯焊盘或旗座(flag)。在管芯键合工艺中,布置于管芯和支撑件之间的粘性键合材料固化。典型的键合材料是聚合物粘合剂,例如,环氧树脂、软焊料或共晶合金。
在管芯键合操作期间,键合材料可以向上流到管芯的边缘,形成填角(fillet)。填角的高度是一个生产变量,控制该生产变量是重要的。为了提高封装密度,半导体管芯的厚度被最小化。例如,可以在半导体管芯的切单之前磨削晶片的背面以减小晶片的厚度。但是,减小管芯厚度增加了填角高度变得过大的风险;也就是,其中管芯键合材料溢出管芯的边缘并且流到管芯的有源面之上,这继而又能够引起丝线键合的缺陷(例如,管芯上的接触焊盘的短路)的情形。因而,能够精确地控制填角高度并且从而防止管芯键合材料流到管芯的有源面之上将是有利的。
附图说明
本发明以实例的方式示出并且不受其示出于附图中的实施例限制,在附图中相同的参考符号指示相似的元件。在附图中的元件仅出于简明和清晰器起见而示出,并不一定要按比例画出。
图1是具有与管芯支撑元件键合的半导体管芯的常规半导体器件的示意性截面图;
图2是根据本发明的一种实施例(以实例的方式给出的)的具有与管芯支撑元件键合的半导体管芯的半导体器件的示意性截面图;以及
图3到图7是根据本发明的一种实施例(以实例的方式给出的)的图2的半导体器件在组装或封装过程中的各个阶段的截面图。
具体实施方式
用于表面安装的半导体器件封装具有暴露的电接触。暴露的电接触在内部与半导体管芯的有源面上的电接触焊盘连接。可使用各种技术来使封装的暴露电接触与嵌入的半导体管芯连接。在附图中示出的半导体器件是丝线键合的封装,在该封装中半导体管芯安装于管芯支撑件上,半导体管芯的有源面与管芯支撑件相反。丝线然后键合至半导体管芯的接触焊盘以及至封装的暴露电接触以提供内部连接。但是,所示出并描述的将管芯键合于管芯支撑件上的实例同样可应用于其他的半导体器件封装结构。
图1示出了一种已知的封装半导体器件100。半导体器件100包括具有相反的第一面42和第二面44以及边缘表面46的半导体管芯40。半导体管芯40的第一面42是有源面并且具有多个电接触元件(没有示出)。半导体管芯40的第二面44以管芯附接材料52(例如,环氧物)附接于管芯支撑部件51。在管芯的第一面42上的电接触元件以键合丝线54电连接至管芯支撑件51上的暴露电接触元件(没有示出)以用于与外部电路的连接。管芯40和键合丝线51以模塑料(moldingcompound)56覆盖。
在半导体管芯40与管芯支撑件51键合期间,管芯附接材料52是粘性的。当将半导体管芯40的第二面44施加于管芯附接材料52时,会促使管芯附接材料52外流超出管芯40的边缘表面46以保证完全覆盖第二面44并降低半导体管芯40倾斜的风险。然后,表面张力促使管芯附接材料52向上流到边缘表面46,形成填角50。如果填角50具有过大的高度,这将会表现出管芯附接材料52流过管芯边缘46并且流到了有源面42之上,伴随有引起诸如在管芯40上的接触焊盘短路的缺陷的风险。如果边缘表面46是平坦的,使得半导体管芯40的截面是矩形的,则管芯附接材料52将向上直流到管芯的边缘表面46。为了降低管芯附接材料52溢出到有源面42之上的风险,已知的半导体器件100具有形成于管芯边缘表面46中的台阶48。台阶48形成于半导体管芯40的第一面42中。管芯附接材料52能够在溢出到有源面42上之前流过台阶48的距离大于在直边缘表面46的情形中的距离。但是,台阶减小了有源面42的宽度,使得该宽度小于相反面44的宽度,这具有减少每一晶片的管芯数和/或减少能够位于活性面42之上的电接触元件的数量的缺点。此外,当管芯附接材料52流过台阶48时,表面张力将会促使管芯附接材料52仍旧朝上流向有源面42,留下了管芯附接材料52溢出到有源面42之上的一定风险。
图2示出了根据本发明的一种实施例的半导体器件200的实例。半导体器件200包括具有相反的第一面204和第二面206以及边缘表面208的半导体管芯202。半导体器件200还包括具有键合表面212的管芯支撑部件210,例如引线框的导热旗座。半导体管芯202在边缘208具有位于第一面204下方或之下的底切214。
半导体管芯202的第二面206键合至管芯支撑部件210的具有管芯附接材料的键合表面212,其中管芯附接材料的填角216形成于由底切214限定的区域之内。
在将半导体管芯202的第二面206键合至键合表面212的过程期间,底切214含有管芯附接材料使得填角216没有延伸过管芯外缘208且流到管芯的第一面204之上。即使填角216的尺寸过大,管芯附接材料将由键合表面212的通常平行于底切214的悬突的表面张力吸引而倾向于向外流动,而不是沿着垂直的边缘表面208朝上流向第一面204,从而降低了管芯附接材料溢出到第一面204之上和引起缺陷的风险。
第一面204是半导体管芯202的有源面并且具有大于第二面206的宽度,与半导体器件100相比,这能够允许增加每一晶片的管芯202的数量和/或增加在管芯202的第一正面(有源面)204上的电接触元件的数量。
半导体器件200包括一组暴露的电接触元件218,暴露的电接触元件218可以由引线框的一部分来形成,引线框还提供了管芯支撑件210。半导体管芯202的有源面204具有与暴露的电接触元件218(例如,与键合丝线222)电连接的多个电接触元件220,这可以使用已知的丝线键合工艺和设备来完成。模塑料224覆盖第一面204、填角216和键合丝线222。
应当意识到,诸如器件200的半导体器件可以包括多于一个的半导体管芯202,该半导体管芯202的每一个的边缘表面208包括底切214。
为了清晰起见,在附图中的垂直尺寸已经相对于水平尺寸进行了放大。举例来说,在半导体管芯202的一种实例中,通过在切单管芯之前对晶片进行背研磨来使管芯202的厚度减小至125μm。底切214为50μm宽和75μm高。
图3到图7示出了根据本发明的一种实施例的一种制作半导体器件(例如,器件200)的方法的实例。该方法开始先提供在其中形成半导体电路的晶片300。图3是晶片300的一部分的截面图,所示出的这部分包括用于两个相邻的半导体管芯202的部分的材料。图3到图7所示的方法包括提供具有相反的第一面204和第二面206以及边缘表面208的半导体管芯202。管芯的边缘表面208具有形成于第一面204下方或之下的底切214。如前面所讨论的,底切214的作用是防止管芯附接材料流到管芯202的第一面(有源面)204之上,使得管芯附接材料不妨碍在管芯202的第一面(有源面)上的电连接和电接触元件。
再次参考图3,图3所示的晶片300的顶面形成了半导体管芯202的第一面204。图3所示的晶片300的底面或背面在背研磨之后形成了半导体管芯202的第二面206。第一面204包括多个电接触元件220。图3所示的晶片300的顶面还给出了对准标记(没有示出),用于引导切单和其他锯切操作。
如图4所示,晶片300然后被翻转并且被安装使半导体管芯202的第一面204在背衬(backing)400(例如,粘合剂支撑膜)之上。
如图5所示,在背衬400上的晶片300安置于锯机内。锯机在附图中由第一锯片500和摄像机502来表示。介于晶片300和摄像机502之间的背衬和任何卡台对摄像机502及锯机的引导系统而言都是透明的。第一锯片500由椭圆形象征性地表示,但是应当意识到,旋转锯片500实际上应当是具有任意适合的截面的圆形。第一锯片500被用来形成在晶片300的背面上的第一切口以形成凹槽504,该凹槽504部分路径通过在半导体管芯202的第二面206中的晶片300的厚度。凹槽504被示出为具有矩形截面,但是应当理解,凹槽504可以具有任意适合的截面,这将通常由旋转锯片500的截面来限定。
第一锯片500沿着在相邻的半导体管芯202之间的一组平行锯道和一组正交的平行锯道位移以形成凹槽504。第一锯片500的位移由在晶片300的第一面204上的对准标记来引导,该对准标记由摄像机502感测。凹槽504的宽度S1由第一锯片500的宽度限定。每个凹槽504将形成相邻的半导体管芯202的底切214。凹槽504的宽度S1大于两个相邻底切214的宽度,以允许半导体管芯202随后的切单。
如图6所示,在本发明的一种实施例的这个实例中,半导体管芯202然后被切单。第一锯片500替换为第二锯片600并且第二锯片600被用来形成沿着在相邻的半导体管芯202之间的同一组平行锯道和同一组正交的平行锯道的第二切口,该第二锯片600仍由在晶片300的顶面上的对准标记来引导,该对准标记由摄像机502感测。第二锯片600的宽度S2小于第一锯片500的宽度S1。第二锯片600在凹槽504中从与半导体管芯202的第二面206相同的一侧整体上切割通过晶片300的剩余厚度,以便对半导体管芯202切单。
如图7所示,支撑材料700(例如,粘合剂支撑膜)在切单之后被施加于半导体管芯202的第二面206并且在第一面204上的背衬400被去除。在支撑材料700上的半导体管芯202然后被反转或被翻转并且然后由本技术领域中已知的拾放工具从支撑材料700单个地拾起。然后,每个半导体管芯202以管芯附接粘合剂附接于管芯支撑部件210的键合表面212并且填角216形成于底切214之内。
在该实例中,管芯附接粘合剂被施加于管芯支撑件210的键合表面212。然后,半导体管芯202的第二面206被施加于管芯附接材料,管芯附接材料流入由凹槽504形成的底切214内,从而形成了填角216。在本发明的另一实施例的一个实例中,管芯附接材料被施加于半导体管芯202的第二面206并且管芯202然后被施加于管芯支撑件210的键合表面212,并且填角216再一次形成于底切214之内。
在将半导体管芯202附接于管芯支撑件210的键合表面212之后,例如以使用市场上可购得的丝线键合设备的已知的丝线键合工艺来使管芯202的电接触元件220与暴露的电接触元件218中对应的那些电连接。在丝线键合之后,执行包封,管芯202、键合丝线222和填角216由模塑料224覆盖。
在切割凹槽504的同一台机器上执行晶片300的切单是方便的。在该方法的这个实例中,同时使用两个宽度不同的锯片,以不同的锯片高度在不同的锯道中切割。作为选择,将较宽的锯片改变成较窄的锯片并且调整锯片高度将是可能的。但是,在本发明的另一实施例的另一实例中,在切割凹槽504之后,晶片300被安装于背衬700上。随后通过锯切、划片或激光切割来执行晶片300的切单。
在前面的说明中,本发明已经针对本发明的实施例的具体实例进行了描述。但是,明显的是,在不脱离所附权利要求书所阐述的本发明更广泛的精神和范围的情况下可以进行各种修改和改变。例如,在此所描述的半导体管芯202能够是任意半导体材料或材料组合,例如砷化镓、锗硅、绝缘体上硅(SOI)、硅、单晶硅等,以及以上这些的组合。
词语“前面”、“后面”、“顶部”、“底部”、“上方”、“下方”等在说明书和权利要求书中用于叙述性的作用并且不一定描述不变的相对位置。应当理解,这样使用的词语在适当的情况下是可互换的,使得例如本发明在此所描述的实施例能够按照与此所示出的或另外描述的那些取向不同的取向来操作。
此外,本领域技术人员应当意识到,在以上所描述的操作之间的界限只是例示性的。因而,说明书和附图因此将被看作是说明性的而不是限制性的。

Claims (10)

1.一种组装半导体器件的方法,包括以下步骤:
提供具有相反的第一面和第二面以及边缘表面的半导体管芯,其中所述边缘表面具有在所述第一面下的底切,并且其中所述第一面是所述半导体管芯的有源面且具有大于所述第二面的宽度;
提供具有键合表面的管芯支撑部件;以及
以管芯附接材料将所述半导体管芯附接于所述键合表面,其中所述管芯附接材料流入所述底切中并且在所述底切中形成填角。
2.根据权利要求1所述的方法,其中将所述半导体管芯附接于所述键合表面的步骤包括将所述管芯附接材料施加于所述键合表面,以及将所述半导体管芯的所述第二面施加于所述管芯附接材料。
3.根据权利要求1所述的方法,其中所述半导体器件具有多个暴露的电接触元件并且所述半导体管芯具有多个在所述有源面上的电接触元件,所述方法还包括将所述管芯的所述电接触元件与所述暴露的电接触元件电连接的步骤。
4.根据权利要求3所述的方法,其中将所述管芯的所述电接触元件与所述暴露电接触元件电连接的步骤包括将丝线键合至所述电接触元件。
5.根据权利要求4所述的方法,还包括以模塑料包封所述半导体管芯、键合丝线和填角,其中所述第一面嵌入到所述模塑料中。
6.根据权利要求1所述的方法,其中提供所述半导体管芯的步骤包括安装半导体材料的晶片使所述管芯的所述第一面在背衬材料上,用具有第一宽度的第一锯片执行第一锯切操作以形成所述底切,其中所述第一锯切操作包括部分地锯切通过所述晶片,以及用具有小于所述第一宽度的第二宽度的第二锯片执行第二锯切操作,其中所述第二锯切操作对所述半导体管芯切单。
7.根据权利要求6所述的方法,其中所述晶片包括在所述管芯的所述第一面上的对准标记,所述对准标记用于在所述第一锯切操作期间引导所述第一锯片。
8.根据权利要求6所述的方法,还包括背研磨所述晶片以产生所述管芯的所述第二面。
9.一种半导体管芯,包括:
相反的第一面和第二面以及边缘表面,其中所述边缘表面包括在所述第一面下的底切,在将所述第二面键合于键合表面期间管芯附接材料能够流入所述底切内使得所述管芯附接材料的填充物形成于所述底切之内;以及
多个电接触元件,用于与封装器件的相应多个暴露的电接触元件连接,所述电接触元件被布置于所述第一面上。
10.一种半导体器件,包括:
具有相反的第一面和第二面以及边缘表面的半导体管芯,其中所述边缘表面包括在所述第一面下的底切,其中所述第一面是所述半导体管芯的有源面,并且其中所述第一面具有大于所述第二面的宽度;
具有键合表面的管芯支撑元件,其中所述半导体管芯的所述第二面以管芯附接材料附接于所述键合表面,其中所述管芯附接材料的填角形成于所述底切中;
多个暴露的电接触元件,其中所述半导体管芯的所述有源面具有与所述暴露的电接触元件电连接的相应的多个电接触元件,并且其中所述管芯的所述电接触元件被用键合丝线与所述暴露的电接触元件电连接;以及
模塑料,至少覆盖所述半导体管芯的所述第一面、所述键合丝线和所述填角。
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Cited By (3)

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Families Citing this family (7)

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US20130157414A1 (en) * 2011-12-20 2013-06-20 Nxp B. V. Stacked-die package and method therefor
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* Cited by examiner, † Cited by third party
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US20020096766A1 (en) * 2001-01-24 2002-07-25 Chen Wen Chuan Package structure of integrated circuits and method for packaging the same
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