JP6042384B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 104
- 239000004065 semiconductor Substances 0.000 title claims description 77
- 238000000034 method Methods 0.000 claims description 156
- 238000012937 correction Methods 0.000 claims description 68
- 239000004020 conductor Substances 0.000 claims description 54
- 230000003287 optical effect Effects 0.000 claims description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 1
- 238000012545 processing Methods 0.000 description 247
- 238000013461 design Methods 0.000 description 206
- 235000012431 wafers Nutrition 0.000 description 92
- 238000003672 processing method Methods 0.000 description 18
- 238000004088 simulation Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000006870 function Effects 0.000 description 6
- 238000004364 calculation method Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000003466 anti-cipated effect Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000008961 swelling Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 238000001015 X-ray lithography Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
- G03F7/70441—Optical proximity correction [OPC]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
-
- E—FIXED CONSTRUCTIONS
- E21—EARTH OR ROCK DRILLING; MINING
- E21B—EARTH OR ROCK DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
- E21B43/00—Methods or apparatus for obtaining oil, gas, water, soluble or meltable materials or a slurry of minerals from wells
- E21B43/16—Enhanced recovery methods for obtaining hydrocarbons
- E21B43/24—Enhanced recovery methods for obtaining hydrocarbons using heat, e.g. steam injection
-
- E—FIXED CONSTRUCTIONS
- E21—EARTH OR ROCK DRILLING; MINING
- E21B—EARTH OR ROCK DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
- E21B47/00—Survey of boreholes or wells
- E21B47/06—Measuring temperature or pressure
-
- E—FIXED CONSTRUCTIONS
- E21—EARTH OR ROCK DRILLING; MINING
- E21B—EARTH OR ROCK DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
- E21B47/00—Survey of boreholes or wells
- E21B47/12—Means for transmitting measuring-signals or control signals from the well to the surface, or from the surface to the well, e.g. for logging while drilling
- E21B47/13—Means for transmitting measuring-signals or control signals from the well to the surface, or from the surface to the well, e.g. for logging while drilling by electromagnetic energy, e.g. radio frequency
- E21B47/135—Means for transmitting measuring-signals or control signals from the well to the surface, or from the surface to the well, e.g. for logging while drilling by electromagnetic energy, e.g. radio frequency using light waves, e.g. infrared or ultraviolet waves
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mining & Mineral Resources (AREA)
- Life Sciences & Earth Sciences (AREA)
- Geology (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Fluid Mechanics (AREA)
- General Life Sciences & Earth Sciences (AREA)
- Geochemistry & Mineralogy (AREA)
- Environmental & Geological Engineering (AREA)
- Remote Sensing (AREA)
- General Physics & Mathematics (AREA)
- Geophysics (AREA)
- General Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Electromagnetism (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Electron Beam Exposure (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
実施の形態1に係る半導体装置およびその製造方法ならびに半導体製造用マスク、光近接処理方法においては、ランダムロジック回路に対応するランダムロジック領域において、高精度な処理を必要としない領域については低精度な処理を行うことを特徴とする。このような精度の調整は、設計レイアウトに対してOPC(Optical Proximity Correction:光近接補正)を行うことによりOPC後レイアウトを生成する既存のEDA(Electrical Design Automation)ツールにおいて設定を調整することにより実施できる。これにより、処理時間を短縮し製造コストを低減することが可能となる。
実施の形態1においては、低精度な処理が可能なレイアウトとして、図12を用いて、導電体層に含まれるダミーレイアウトを抽出する手法について説明した。実施の形態2においては、導電体層のうち、ダミーレイアウト以外のレイアウトであって、低精度な処理が可能なものについて説明する。
実施の形態1〜2においては、低精度な処理が可能なレイアウトとして、図12および図20を用いて、導電体層のうち低精度な処理が可能な領域について説明した。実施の形態3においては、活性層のうち、低精度な処理が可能な領域について説明する。
実施の形態3においては、低精度な処理が可能なレイアウトとして、図21および図22を用いて、活性層のうち低精度な処理が可能な領域について説明した。実施の形態4においては、配線層(配線領域)のうち、低精度な処理が可能な領域について説明する。
実施の形態4においては、低精度な処理が可能なレイアウトとして、図23を用いて、配線層のうち低精度な処理が可能な領域について説明した。実施の形態5においては、ホール層のうち、低精度な処理が可能な領域について説明する。
実施の形態1〜5においては、DRCの基本的な機能を用いることにより処理精度を低くする手法について説明した。実施の形態6においては、互いに類似した形状を有する複数種類の設計パターンを1種類のOPC後パターンに揃える(マージする)ことにより処理精度を低くする手法について説明する。
実施の形態6においては、互いに類似した形状を有する複数種類の設計パターンを1種類のOPC後パターンにマージすることにより処理精度を低くする手法について説明した。しかし、実施の形態6においては、互いに類似した形状を有する複数種類の設計パターン全てにOPC処理を行った後にマージするので、マスク描画時間は短縮できても、OPC処理に伴う負荷はあまり低減できない場合がある。実施の形態7においては、OPC処理に伴う負荷を低減しつつ処理精度を低くする手法について説明する。
Claims (3)
- ロジック回路を含む半導体装置の製造方法であって、
前記ロジック回路の光近接補正後レイアウトを用いて所定の精度で露光処理を行うことによりマスク上に前記ロジック回路の第1レイアウトを生成する工程(a)と、
前記ロジック回路の光近接補正後レイアウトを用いて前記所定の精度より低い精度で露光処理を行うことによりマスク上に前記ロジック回路の第2レイアウトを生成する工程(b)と、
前記工程(a)および前記工程(b)から得られた光近接補正後レイアウトパターンから生成されたフォトマスクを用いてフォトレジストを塗布した半導体基板上に前記レイアウトパターンを転写する工程と
を備え、
前記第1レイアウトは、トランジスタとして動作するゲート配線を有し、
前記第2レイアウトは、トランジスタとして動作しないダミーゲート配線を有し、
前記ゲート配線は、活性領域との重なりを有し、
前記ダミーゲート配線は、前記活性領域との重なりを有さない導電体層である
半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法であって、
前記第1レイアウトにおいて、前記ゲート配線は第1ピッチで形成され、
前記第2レイアウトにおいて、前記ダミーゲート配線は第2ピッチで形成される
半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法であって、
前記第1ピッチと前記第2ピッチとは略同一である
半導体装置の製造方法。
Priority Applications (1)
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JP2014167172A JP6042384B2 (ja) | 2005-04-26 | 2014-08-20 | 半導体装置の製造方法 |
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JP2005127798 | 2005-04-26 | ||
JP2005127798 | 2005-04-26 | ||
JP2014167172A JP6042384B2 (ja) | 2005-04-26 | 2014-08-20 | 半導体装置の製造方法 |
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JP2012127170A Division JP5841009B2 (ja) | 2005-04-26 | 2012-06-04 | 半導体装置の製造方法 |
Publications (2)
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JP2015028636A JP2015028636A (ja) | 2015-02-12 |
JP6042384B2 true JP6042384B2 (ja) | 2016-12-14 |
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JP2007514733A Active JP5225676B2 (ja) | 2005-04-26 | 2006-04-25 | 半導体装置およびその製造方法ならびに半導体製造用マスク、光近接処理方法 |
JP2012127170A Active JP5841009B2 (ja) | 2005-04-26 | 2012-06-04 | 半導体装置の製造方法 |
JP2014167172A Active JP6042384B2 (ja) | 2005-04-26 | 2014-08-20 | 半導体装置の製造方法 |
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JP2012127170A Active JP5841009B2 (ja) | 2005-04-26 | 2012-06-04 | 半導体装置の製造方法 |
Country Status (6)
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US (3) | US8103977B2 (ja) |
JP (3) | JP5225676B2 (ja) |
KR (2) | KR101275682B1 (ja) |
CN (4) | CN101213489B (ja) |
TW (1) | TWI463246B (ja) |
WO (1) | WO2006118098A1 (ja) |
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CN104882442A (zh) | 2015-09-02 |
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US8719740B2 (en) | 2014-05-06 |
JP5225676B2 (ja) | 2013-07-03 |
US8103977B2 (en) | 2012-01-24 |
TWI463246B (zh) | 2014-12-01 |
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US8458627B2 (en) | 2013-06-04 |
KR20120074337A (ko) | 2012-07-05 |
JP2012212154A (ja) | 2012-11-01 |
CN104090466A (zh) | 2014-10-08 |
CN101213489B (zh) | 2015-05-13 |
JP5841009B2 (ja) | 2016-01-06 |
CN104882442B (zh) | 2018-09-11 |
CN102610606A (zh) | 2012-07-25 |
US20130249597A1 (en) | 2013-09-26 |
TW200731002A (en) | 2007-08-16 |
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