JP5990421B2 - 配線基板及びその製造方法、半導体パッケージ - Google Patents

配線基板及びその製造方法、半導体パッケージ Download PDF

Info

Publication number
JP5990421B2
JP5990421B2 JP2012161067A JP2012161067A JP5990421B2 JP 5990421 B2 JP5990421 B2 JP 5990421B2 JP 2012161067 A JP2012161067 A JP 2012161067A JP 2012161067 A JP2012161067 A JP 2012161067A JP 5990421 B2 JP5990421 B2 JP 5990421B2
Authority
JP
Japan
Prior art keywords
insulating layer
insulating
layer
wiring
mainly composed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012161067A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014022618A5 (enExample
JP2014022618A (ja
Inventor
中村　順一
順一 中村
道郎 尾川
道郎 尾川
小林　和弘
和弘 小林
浩巳 伝田
浩巳 伝田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2012161067A priority Critical patent/JP5990421B2/ja
Priority to US13/936,443 priority patent/US9232642B2/en
Priority to TW102124656A priority patent/TWI593333B/zh
Priority to KR1020130082572A priority patent/KR101968957B1/ko
Publication of JP2014022618A publication Critical patent/JP2014022618A/ja
Publication of JP2014022618A5 publication Critical patent/JP2014022618A5/ja
Application granted granted Critical
Publication of JP5990421B2 publication Critical patent/JP5990421B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/695—Organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/257—Arrangements for cooling characterised by their materials having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh or porous structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/259—Ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP2012161067A 2012-07-20 2012-07-20 配線基板及びその製造方法、半導体パッケージ Active JP5990421B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2012161067A JP5990421B2 (ja) 2012-07-20 2012-07-20 配線基板及びその製造方法、半導体パッケージ
US13/936,443 US9232642B2 (en) 2012-07-20 2013-07-08 Wiring substrate, method for manufacturing the wiring substrate, and semiconductor package
TW102124656A TWI593333B (zh) 2012-07-20 2013-07-10 配線基板、配線基板之製造方法以及半導體封裝
KR1020130082572A KR101968957B1 (ko) 2012-07-20 2013-07-15 배선 기판 및 그 제조 방법, 반도체 패키지

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012161067A JP5990421B2 (ja) 2012-07-20 2012-07-20 配線基板及びその製造方法、半導体パッケージ

Publications (3)

Publication Number Publication Date
JP2014022618A JP2014022618A (ja) 2014-02-03
JP2014022618A5 JP2014022618A5 (enExample) 2015-08-13
JP5990421B2 true JP5990421B2 (ja) 2016-09-14

Family

ID=49945891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012161067A Active JP5990421B2 (ja) 2012-07-20 2012-07-20 配線基板及びその製造方法、半導体パッケージ

Country Status (4)

Country Link
US (1) US9232642B2 (enExample)
JP (1) JP5990421B2 (enExample)
KR (1) KR101968957B1 (enExample)
TW (1) TWI593333B (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014127623A (ja) * 2012-12-27 2014-07-07 Shinko Electric Ind Co Ltd 配線基板及び配線基板の製造方法
JP6161380B2 (ja) * 2013-04-17 2017-07-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6435893B2 (ja) * 2015-02-04 2018-12-12 大日本印刷株式会社 貫通電極基板の製造方法
US9961767B2 (en) * 2015-02-10 2018-05-01 Shinko Electric Industires Co., Ltd. Circuit board and method of manufacturing circuit board
KR101776397B1 (ko) 2015-09-09 2017-09-07 고승용 압력게이지 보호용 밸브장치
JP6661232B2 (ja) * 2016-03-01 2020-03-11 新光電気工業株式会社 配線基板、半導体装置、配線基板の製造方法及び半導体装置の製造方法
JP6594264B2 (ja) * 2016-06-07 2019-10-23 新光電気工業株式会社 配線基板及び半導体装置、並びにそれらの製造方法
JP6705718B2 (ja) 2016-08-09 2020-06-03 新光電気工業株式会社 配線基板及びその製造方法
TWI719241B (zh) * 2017-08-18 2021-02-21 景碩科技股份有限公司 可做電性測試的多層電路板及其製法
JP2019041041A (ja) * 2017-08-28 2019-03-14 新光電気工業株式会社 配線基板、半導体装置、配線基板の製造方法及び半導体装置の製造方法
US10854550B2 (en) 2017-09-28 2020-12-01 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
JP7289620B2 (ja) * 2018-09-18 2023-06-12 新光電気工業株式会社 配線基板、積層型配線基板、半導体装置
TWI745162B (zh) * 2020-11-12 2021-11-01 力成科技股份有限公司 半導體封裝結構
KR20220151431A (ko) * 2021-05-06 2022-11-15 삼성전기주식회사 인쇄회로기판
KR20230055561A (ko) 2021-10-19 2023-04-26 삼성전기주식회사 인쇄회로기판 및 이를 포함하는 전자부품 패키지
CN117790327A (zh) * 2022-09-19 2024-03-29 星科金朋私人有限公司 半导体器件及其制造方法
TWI819835B (zh) * 2022-10-05 2023-10-21 華東科技股份有限公司 晶片封裝結構
TWI835561B (zh) * 2023-02-16 2024-03-11 大陸商芯愛科技（南京）有限公司 電子封裝件及其封裝基板與製法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0791096B2 (ja) 1990-08-30 1995-10-04 川崎重工業株式会社 粉粒状原料の流動層焼成方法および装置
JPH09237972A (ja) 1996-02-29 1997-09-09 Kyocera Corp 多層配線基板
JP3537620B2 (ja) 1997-02-27 2004-06-14 京セラ株式会社 多層配線基板
US7321098B2 (en) * 2004-04-21 2008-01-22 Delphi Technologies, Inc. Laminate ceramic circuit board and process therefor
JP4108643B2 (ja) 2004-05-12 2008-06-25 日本電気株式会社 配線基板及びそれを用いた半導体パッケージ
JP2006237324A (ja) 2005-02-25 2006-09-07 Seiko Epson Corp 半導体装置及びその製造方法
JP5295596B2 (ja) * 2008-03-19 2013-09-18 新光電気工業株式会社 多層配線基板およびその製造方法
JP4473935B1 (ja) * 2009-07-06 2010-06-02 新光電気工業株式会社 多層配線基板
JP5444136B2 (ja) * 2010-06-18 2014-03-19 新光電気工業株式会社 配線基板
JP5578962B2 (ja) * 2010-06-24 2014-08-27 新光電気工業株式会社 配線基板
JP5449413B2 (ja) * 2012-01-16 2014-03-19 日本特殊陶業株式会社 多層配線基板

Also Published As

Publication number Publication date
TW201422084A (zh) 2014-06-01
KR101968957B1 (ko) 2019-04-15
JP2014022618A (ja) 2014-02-03
TWI593333B (zh) 2017-07-21
US9232642B2 (en) 2016-01-05
KR20140011946A (ko) 2014-01-29
US20140021625A1 (en) 2014-01-23

Similar Documents

Publication Publication Date Title
JP5990421B2 (ja) 配線基板及びその製造方法、半導体パッケージ
JP6169955B2 (ja) 配線基板及びその製造方法
JP6133227B2 (ja) 配線基板及びその製造方法
JP5715835B2 (ja) 半導体パッケージ及びその製造方法
JP5886617B2 (ja) 配線基板及びその製造方法、半導体パッケージ
JP5649490B2 (ja) 配線基板及びその製造方法
JP6358887B2 (ja) 支持体、配線基板及びその製造方法、半導体パッケージの製造方法
JP6375159B2 (ja) 配線基板、半導体パッケージ
JP6594264B2 (ja) 配線基板及び半導体装置、並びにそれらの製造方法
JP6054080B2 (ja) 支持体及びその製造方法、配線基板の製造方法、電子部品装置の製造方法、配線構造体
JP6705718B2 (ja) 配線基板及びその製造方法
JP6341714B2 (ja) 配線基板及びその製造方法
JP6761064B2 (ja) 配線基板及びその製造方法
JP5406572B2 (ja) 電子部品内蔵配線基板及びその製造方法
JP2009152282A (ja) 集合配線基板及び半導体パッケージ
JP7046639B2 (ja) 配線基板及びその製造方法
JP2019016683A (ja) 配線基板及びその製造方法、半導体パッケージ
JP6671256B2 (ja) 配線基板及びその製造方法
JP2013030808A (ja) 配線基板製造用の仮基板及びその製造方法
JP2018195600A (ja) 配線基板、配線基板の製造方法
JP2013080823A (ja) プリント配線板及びその製造方法
JP5223973B1 (ja) プリント配線板及びプリント配線板の製造方法
JP2008181920A (ja) 電子部品内蔵基板とこれを用いた電子機器、およびその製造方法
JP2012114110A (ja) 多層配線基板の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150623

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150623

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160420

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160510

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160705

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160802

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160815

R150 Certificate of patent or registration of utility model

Ref document number: 5990421

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150