JP6671256B2 - 配線基板及びその製造方法 - Google Patents
配線基板及びその製造方法 Download PDFInfo
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- JP6671256B2 JP6671256B2 JP2016136291A JP2016136291A JP6671256B2 JP 6671256 B2 JP6671256 B2 JP 6671256B2 JP 2016136291 A JP2016136291 A JP 2016136291A JP 2016136291 A JP2016136291 A JP 2016136291A JP 6671256 B2 JP6671256 B2 JP 6671256B2
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- layer
- wiring
- electronic component
- insulating film
- electrode
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Description
[第1の実施の形態に係る配線基板の構造]
まず、第1の実施の形態に係る配線基板の構造について説明する。図1は、第1の実施の形態に係る配線基板を例示する図であり、図1(a)は断面図、図1(b)は図1(a)のA部周辺の部分拡大平面図である。但し、図1(b)において、第1配線層10、絶縁層20、及びソルダーレジスト層60の図示を省略している。
次に、第1の実施の形態に係る配線基板の製造方法について説明する。図2〜図5は、第1の実施の形態に係る配線基板の製造工程を例示する図である。本実施の形態では、支持体上に複数の配線基板となる部分を作製し支持体を除去後個片化して各配線基板とする工程の例を示すが、支持体上に1個ずつ配線基板を作製し支持体を除去する工程としてもよい。
第1の実施の形態の変形例1では、接続用配線12に貫通孔12xを形成しない例を示す。なお、第1の実施の形態の変形例1において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第1の実施の形態の変形例2では、電子部品30を内蔵する絶縁層の構造が異なる例を示す。なお、第1の実施の形態の変形例2において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
配線基板の応用例1では、第1の実施の形態に係る配線基板に半導体チップが搭載(フリップチップ実装)された半導体パッケージの例を示す。なお、配線基板の応用例1において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
配線基板の応用例2では、配線基板の応用例1の電子部品30に代えて電子部品200を内蔵した半導体パッケージの例を示す。なお、配線基板の応用例2において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
4、5 半導体パッケージ
10 第1配線層
11 微細配線
12 接続用配線
12x、14x、21x、41x、53x 貫通孔
20、20A 絶縁層
20x、20y、20z ビアホール
21 第1絶縁膜
22、23 第2絶縁膜
23x 電子部品収容部
24 第3絶縁膜
25 補強材
30、200 電子部品
31 本体
32 電極
40 第2配線層
41、51、53 第1層
42、52、54 第2層
43、55 第3層
50、50A 第3配線層
60、70 ソルダーレジスト層
60x、70x 開口部
100 半導体チップ
110 電極パッド
120 バンプ
130 アンダーフィル樹脂
140 外部接続端子
210、230、250 半導体チップ
220、240、260 貫通電極
270、280 接合部
400 支持体
408 キャリア付き金属箔
409 厚箔
410、530 薄箔
Claims (11)
- 絶縁層と、
前記絶縁層に内蔵された電子部品と、
前記絶縁層に形成され、前記絶縁層の一方の面側に開口し、前記電子部品の電極を露出するビアホールと、
前記絶縁層に埋め込まれ、一方の面が前記絶縁層の一方の面から露出する第1配線層と、
前記第1配線層の一方の面に形成された配線パターン、及び前記配線パターンから前記ビアホール内に延在して前記電子部品の電極と直接接続されたビア配線、を含む第2配線層と、を有し、
前記絶縁層は、前記第1配線層を埋め込む第1絶縁膜、及び前記電子部品を内蔵する第2絶縁膜が積層された構造であり、
前記第1絶縁膜は、全ての前記第1配線層の側面及び他方の面、並びに前記ビア配線の側面の一部を被覆し、
前記電子部品の電極は、前記ビア配線と接する面が前記第2絶縁膜から露出し、側面が前記第2絶縁膜に被覆され、
前記ビア配線が前記配線パターンと一体である配線基板。 - 前記ビアホールは、前記電子部品の電極上に位置する前記第1配線層、及び前記第1配線層と前記電子部品の電極との間に位置する前記絶縁層を貫通して前記電子部品の電極の一方の面を露出する請求項1に記載の配線基板。
- 前記第2配線層は、
前記第1配線層の一方の面に直接形成され、前記ビアホールと連通する貫通孔を備えた第1層と、
前記第1層上に形成され、前記第1層上から延在して前記貫通孔及び前記ビアホールの内壁に沿って形成され、更に前記ビアホール内に露出する前記電子部品の電極を被覆する第2層と、
前記第2層上に形成され、前記第2層上から延在して前記第2層が形成された前記貫通孔内及び前記ビアホール内を充填する第3層と、を有する請求項1又は2に記載の配線基板。 - 前記絶縁層の一方の面には前記配線パターンを被覆するソルダーレジスト層が形成され、
前記ソルダーレジスト層は、前記配線パターンを選択的に露出する開口部を備え、
前記開口部内に露出する前記配線パターンは、半導体チップ接続用のパッドである請求項1乃至3の何れか一項に記載の配線基板。 - 前記配線パターンは、前記ビア配線と接続された配線と、前記ビア配線と接続されていない配線と、を含み、
前記ビア配線と接続された配線と、前記ビア配線と接続されていない配線とは同一高さである請求項1乃至4の何れか一項に記載の配線基板。 - 前記絶縁層に形成され、前記絶縁層の他方の面側に開口し、前記電子部品の電極を露出する第2ビアホールと、
前記絶縁層の他方の面に形成された配線パターン、及び前記配線パターンから前記第2ビアホール内に延在して前記電子部品の電極と直接接続されたビア配線、を含む第3配線層と、を有する請求項1乃至5の何れか一項に記載の配線基板。 - 前記第1絶縁膜と前記第2絶縁膜との境界は、前記電子部品の電極の前記ビア配線と接する面と面一である請求項1乃至6の何れか一項に記載の配線基板。
- 最外層が金属箔である支持体を準備し、前記金属箔上に一方の面が前記金属箔と接する第1配線層を形成する工程と、
前記金属箔上に、前記第1配線層の側面及び他方の面を被覆する第1絶縁膜を形成する工程と、
前記第1絶縁膜上に、電子部品を搭載する工程と、
前記第1絶縁膜上に、前記電子部品を被覆する第2絶縁膜を形成する工程と、
前記金属箔を除く前記支持体を除去する工程と、
前記金属箔及び前記第1絶縁膜を貫通すると共に前記電子部品の電極を露出するビアホールを形成する工程と、
前記金属箔上及び前記ビアホール内に金属層を形成後、前記金属箔及び前記金属層をパターニングし、前記金属箔及び前記金属層を備えた配線パターン、及び前記配線パターンから前記ビアホール内に延在して前記電子部品の電極と直接接続されたビア配線、を含む第2配線層を形成する工程と、を有し、
前記第1絶縁膜は、全ての前記第1配線層の側面及び他方の面、並びに前記ビア配線の側面の一部を被覆し、
前記電子部品の電極は、前記ビア配線と接する面が前記第2絶縁膜から露出し、側面が前記第2絶縁膜に被覆され、
前記第2配線層を形成する工程において、前記ビア配線を前記配線パターンと一体に形成する配線基板の製造方法。 - 前記第2配線層を形成する工程は、
前記金属箔の全面、前記ビアホールの内壁面、及び前記ビアホール内に露出する前記電子部品の電極を連続的に被覆するシード層を形成する工程と、
前記シード層を給電層に利用した電解めっき法により、前記シード層上に選択的に電解めっき層を形成する工程と、
前記電解めっき層に覆われていない部分の前記シード層及び前記金属箔をエッチングにより除去する工程と、を有する請求項8に記載の配線基板の製造方法。 - 前記第1配線層を形成する工程では、前記第1配線層の、前記電子部品の電極が配置される予定の領域に、貫通孔を形成しておき、
前記ビアホールを形成する工程では、前記貫通孔に対応する位置の前記金属箔及び前記第1絶縁膜にレーザを照射し、前記電子部品の電極を露出する前記ビアホールを形成する請求項8又は9に記載の配線基板の製造方法。 - 前記第1絶縁膜と前記第2絶縁膜との境界は、前記電子部品の電極の前記ビア配線と接する面と面一となる請求項8乃至10の何れか一項に記載の配線基板の製造方法。
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