JP5957840B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5957840B2
JP5957840B2 JP2011219843A JP2011219843A JP5957840B2 JP 5957840 B2 JP5957840 B2 JP 5957840B2 JP 2011219843 A JP2011219843 A JP 2011219843A JP 2011219843 A JP2011219843 A JP 2011219843A JP 5957840 B2 JP5957840 B2 JP 5957840B2
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Prior art keywords
diameter
etching
wiring
resist pattern
small
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Expired - Fee Related
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JP2011219843A
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English (en)
Japanese (ja)
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JP2013080813A5 (https=
JP2013080813A (ja
Inventor
正永 深沢
正永 深沢
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Sony Corp
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Sony Corp
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Priority to JP2011219843A priority Critical patent/JP5957840B2/ja
Application filed by Sony Corp filed Critical Sony Corp
Priority to US13/617,806 priority patent/US8871633B2/en
Priority to CN201910146438.3A priority patent/CN110060956B/zh
Priority to CN201810824927.5A priority patent/CN109273430B/zh
Priority to CN201210375078.2A priority patent/CN103035615B/zh
Publication of JP2013080813A publication Critical patent/JP2013080813A/ja
Priority to US14/494,134 priority patent/US9293411B2/en
Publication of JP2013080813A5 publication Critical patent/JP2013080813A5/ja
Priority to US14/831,640 priority patent/US9425142B2/en
Priority to US15/193,875 priority patent/US9627359B2/en
Application granted granted Critical
Publication of JP5957840B2 publication Critical patent/JP5957840B2/ja
Priority to US15/474,417 priority patent/US9859214B2/en
Priority to US15/815,023 priority patent/US10157837B2/en
Priority to US16/188,581 priority patent/US10504839B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0257—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising using a sacrificial placeholder, e.g. using a sacrificial plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
JP2011219843A 2011-10-04 2011-10-04 半導体装置の製造方法 Expired - Fee Related JP5957840B2 (ja)

Priority Applications (11)

Application Number Priority Date Filing Date Title
JP2011219843A JP5957840B2 (ja) 2011-10-04 2011-10-04 半導体装置の製造方法
US13/617,806 US8871633B2 (en) 2011-10-04 2012-09-14 Semiconductor device and manufacturing method of the same
CN201910146438.3A CN110060956B (zh) 2011-10-04 2012-09-27 半导体装置的制造方法
CN201810824927.5A CN109273430B (zh) 2011-10-04 2012-09-27 半导体装置及其制造方法
CN201210375078.2A CN103035615B (zh) 2011-10-04 2012-09-27 半导体装置及其制造方法
US14/494,134 US9293411B2 (en) 2011-10-04 2014-09-23 Semiconductor device and manufacturing method of the same
US14/831,640 US9425142B2 (en) 2011-10-04 2015-08-20 Semiconductor device and manufacturing method of the same
US15/193,875 US9627359B2 (en) 2011-10-04 2016-06-27 Semiconductor device and manufacturing method of the same
US15/474,417 US9859214B2 (en) 2011-10-04 2017-03-30 Semiconductor device and manufacturing method of the same
US15/815,023 US10157837B2 (en) 2011-10-04 2017-11-16 Semiconductor device and manufacturing method of the same
US16/188,581 US10504839B2 (en) 2011-10-04 2018-11-13 Semiconductor device and manufacturing method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011219843A JP5957840B2 (ja) 2011-10-04 2011-10-04 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2013080813A JP2013080813A (ja) 2013-05-02
JP2013080813A5 JP2013080813A5 (https=) 2014-11-13
JP5957840B2 true JP5957840B2 (ja) 2016-07-27

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JP2011219843A Expired - Fee Related JP5957840B2 (ja) 2011-10-04 2011-10-04 半導体装置の製造方法

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US (7) US8871633B2 (https=)
JP (1) JP5957840B2 (https=)
CN (3) CN103035615B (https=)

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JP5957840B2 (ja) * 2011-10-04 2016-07-27 ソニー株式会社 半導体装置の製造方法
CN103915462B (zh) * 2014-04-04 2016-11-23 豪威科技(上海)有限公司 半导体器件制备方法以及堆栈式芯片的制备方法
CN104979329B (zh) * 2014-04-10 2018-08-10 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
KR102387948B1 (ko) 2015-08-06 2022-04-18 삼성전자주식회사 Tsv 구조물을 구비한 집적회로 소자
CN108598097A (zh) * 2018-01-09 2018-09-28 德淮半导体有限公司 形成穿通硅通孔结构的方法及形成图像传感器的方法
US11069526B2 (en) * 2018-06-27 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Using a self-assembly layer to facilitate selective formation of an etching stop layer
CN110858597B (zh) * 2018-08-22 2022-03-11 中芯国际集成电路制造（天津）有限公司 硅通孔结构的形成方法、cis晶圆的形成方法及cis晶圆
CN109148361B (zh) * 2018-08-28 2019-08-23 武汉新芯集成电路制造有限公司 半导体器件及其制作方法
CN109449091B (zh) * 2018-11-05 2020-04-10 武汉新芯集成电路制造有限公司 半导体器件的制作方法
CN111261603B (zh) * 2018-11-30 2025-04-25 长鑫存储技术有限公司 用于半导体结构的互连方法与半导体结构
KR102646012B1 (ko) * 2019-02-18 2024-03-13 삼성전자주식회사 반도체 소자 및 이의 제조 방법
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CN114256135A (zh) 2020-09-22 2022-03-29 长鑫存储技术有限公司 开口结构及其形成方法、接触插塞及其形成方法
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CN114256134A (zh) * 2020-09-22 2022-03-29 长鑫存储技术有限公司 接触窗结构及其形成方法
CN114171394B (zh) * 2021-06-18 2025-04-11 李勇 半导体装置的制备方法和半导体装置
CN113764337B (zh) * 2021-11-09 2022-02-22 绍兴中芯集成电路制造股份有限公司 导电插塞的制造方法及半导体结构

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Also Published As

Publication number Publication date
US20190080997A1 (en) 2019-03-14
CN110060956B (zh) 2022-11-18
CN110060956A (zh) 2019-07-26
US20160307877A1 (en) 2016-10-20
CN109273430B (zh) 2023-01-17
US10504839B2 (en) 2019-12-10
CN103035615B (zh) 2020-07-21
US9425142B2 (en) 2016-08-23
US20150008591A1 (en) 2015-01-08
US20150357313A1 (en) 2015-12-10
CN109273430A (zh) 2019-01-25
US8871633B2 (en) 2014-10-28
US20170207163A1 (en) 2017-07-20
US9293411B2 (en) 2016-03-22
US9859214B2 (en) 2018-01-02
CN103035615A (zh) 2013-04-10
US10157837B2 (en) 2018-12-18
US9627359B2 (en) 2017-04-18
US20180076126A1 (en) 2018-03-15
US20130082401A1 (en) 2013-04-04
JP2013080813A (ja) 2013-05-02

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