JP5715835B2 - 半導体パッケージ及びその製造方法 - Google Patents

半導体パッケージ及びその製造方法 Download PDF

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Publication number
JP5715835B2
JP5715835B2 JP2011013180A JP2011013180A JP5715835B2 JP 5715835 B2 JP5715835 B2 JP 5715835B2 JP 2011013180 A JP2011013180 A JP 2011013180A JP 2011013180 A JP2011013180 A JP 2011013180A JP 5715835 B2 JP5715835 B2 JP 5715835B2
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Japan
Prior art keywords
layer
insulating layer
semiconductor package
wiring
wiring layer
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JP2011013180A
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English (en)
Japanese (ja)
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JP2012156251A (ja
JP2012156251A5 (enExample
Inventor
経塚　正宏
正宏 経塚
立岩　昭彦
昭彦 立岩
田中　正人
正人 田中
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2011013180A priority Critical patent/JP5715835B2/ja
Priority to US13/354,663 priority patent/US9142524B2/en
Publication of JP2012156251A publication Critical patent/JP2012156251A/ja
Publication of JP2012156251A5 publication Critical patent/JP2012156251A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
JP2011013180A 2011-01-25 2011-01-25 半導体パッケージ及びその製造方法 Active JP5715835B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011013180A JP5715835B2 (ja) 2011-01-25 2011-01-25 半導体パッケージ及びその製造方法
US13/354,663 US9142524B2 (en) 2011-01-25 2012-01-20 Semiconductor package and method for manufacturing semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011013180A JP5715835B2 (ja) 2011-01-25 2011-01-25 半導体パッケージ及びその製造方法

Publications (3)

Publication Number Publication Date
JP2012156251A JP2012156251A (ja) 2012-08-16
JP2012156251A5 JP2012156251A5 (enExample) 2013-12-26
JP5715835B2 true JP5715835B2 (ja) 2015-05-13

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US (1) US9142524B2 (enExample)
JP (1) JP5715835B2 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11882652B2 (en) 2021-05-06 2024-01-23 Samsung Electro-Mechanics Co., Ltd. Printed circuit board

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US20120090883A1 (en) * 2010-10-13 2012-04-19 Qualcomm Incorporated Method and Apparatus for Improving Substrate Warpage
JP5903337B2 (ja) * 2012-06-08 2016-04-13 新光電気工業株式会社 半導体パッケージ及びその製造方法
CN103730436B (zh) * 2012-10-15 2016-11-16 景硕科技股份有限公司 线路载板的增层结构
JP2014086598A (ja) * 2012-10-24 2014-05-12 Hitachi Chemical Co Ltd 半導体装置の製造方法、半導体装置、及び感光性樹脂組成物
JP6161380B2 (ja) * 2013-04-17 2017-07-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR102250997B1 (ko) 2014-05-02 2021-05-12 삼성전자주식회사 반도체 패키지
US9728498B2 (en) * 2015-06-30 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure
US9711458B2 (en) * 2015-11-13 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method for chip package
GB2561490B (en) 2016-04-07 2019-02-27 Advanced E Textiles Ltd Improvements relating to textiles incorporating electronic devices
US10600748B2 (en) 2016-06-20 2020-03-24 Samsung Electronics Co., Ltd. Fan-out semiconductor package
TWI584425B (zh) * 2016-06-27 2017-05-21 力成科技股份有限公司 扇出型晶圓級封裝結構
JP2018018936A (ja) * 2016-07-27 2018-02-01 イビデン株式会社 配線基板
WO2018031995A1 (en) * 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
JP6291094B2 (ja) * 2017-01-24 2018-03-14 信越化学工業株式会社 積層型半導体装置、及び封止後積層型半導体装置
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US12062700B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
CN118213279A (zh) 2018-07-02 2024-06-18 Qorvo美国公司 Rf半导体装置及其制造方法
CN110783300B (zh) * 2018-07-26 2021-08-13 钰桥半导体股份有限公司 具有调节件及防裂结构的导线架衬底及其覆晶组体
JP7211757B2 (ja) * 2018-10-22 2023-01-24 新光電気工業株式会社 配線基板
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
KR20250027591A (ko) 2019-01-23 2025-02-26 코르보 유에스, 인크. Rf 반도체 디바이스 및 이를 형성하는 방법
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11139179B2 (en) 2019-09-09 2021-10-05 Advanced Semiconductor Engineering, Inc. Embedded component package structure and manufacturing method thereof
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
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US12062571B2 (en) 2021-03-05 2024-08-13 Qorvo Us, Inc. Selective etching process for SiGe and doped epitaxial silicon
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11882652B2 (en) 2021-05-06 2024-01-23 Samsung Electro-Mechanics Co., Ltd. Printed circuit board

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US9142524B2 (en) 2015-09-22
JP2012156251A (ja) 2012-08-16
US20120187557A1 (en) 2012-07-26

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