JP5542256B2 - Ｓｏｉ基板の作製方法 - Google Patents

Ｓｏｉ基板の作製方法 Download PDF

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Publication number
JP5542256B2
JP5542256B2 JP2008278152A JP2008278152A JP5542256B2 JP 5542256 B2 JP5542256 B2 JP 5542256B2 JP 2008278152 A JP2008278152 A JP 2008278152A JP 2008278152 A JP2008278152 A JP 2008278152A JP 5542256 B2 JP5542256 B2 JP 5542256B2
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Prior art keywords
substrate
layer
nitrogen
film
semiconductor
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JP2008278152A
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Japanese (ja)
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JP2009135465A (ja
JP2009135465A5 (enExample
Inventor
哲弥 掛端
和貴 栗城
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008278152A priority Critical patent/JP5542256B2/ja
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Publication of JP2009135465A5 publication Critical patent/JP2009135465A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
JP2008278152A 2007-10-31 2008-10-29 Ｓｏｉ基板の作製方法 Expired - Fee Related JP5542256B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008278152A JP5542256B2 (ja) 2007-10-31 2008-10-29 Ｓｏｉ基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007283669 2007-10-31
JP2007283669 2007-10-31
JP2008278152A JP5542256B2 (ja) 2007-10-31 2008-10-29 Ｓｏｉ基板の作製方法

Publications (3)

Publication Number Publication Date
JP2009135465A JP2009135465A (ja) 2009-06-18
JP2009135465A5 JP2009135465A5 (enExample) 2011-10-06
JP5542256B2 true JP5542256B2 (ja) 2014-07-09

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Family Applications (1)

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JP2008278152A Expired - Fee Related JP5542256B2 (ja) 2007-10-31 2008-10-29 Ｓｏｉ基板の作製方法

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US (3) US7696058B2 (enExample)
JP (1) JP5542256B2 (enExample)
KR (1) KR101497353B1 (enExample)
CN (1) CN101425454B (enExample)
TW (1) TWI470735B (enExample)

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JP2009141093A (ja) 2007-12-06 2009-06-25 Toshiba Corp 発光素子及び発光素子の製造方法
JP5548395B2 (ja) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5663150B2 (ja) * 2008-07-22 2015-02-04 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
KR20120059509A (ko) * 2009-08-25 2012-06-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
JP2011077504A (ja) * 2009-09-02 2011-04-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US8655138B2 (en) 2010-05-10 2014-02-18 Cornell University Waveguide structure and related fabrication method
JP5917036B2 (ja) 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
WO2012129454A2 (en) * 2011-03-24 2012-09-27 Advanced Technology Materials, Inc. Cluster ion implantation of arsenic and phosphorus
FR2975222A1 (fr) * 2011-05-10 2012-11-16 Soitec Silicon On Insulator Procede de fabrication d'un substrat semiconducteur
JP6016532B2 (ja) 2011-09-07 2016-10-26 株式会社半導体エネルギー研究所 半導体装置
US8575666B2 (en) * 2011-09-30 2013-11-05 Raytheon Company Method and structure having monolithic heterogeneous integration of compound semiconductors with elemental semiconductor
WO2014113503A1 (en) * 2013-01-16 2014-07-24 QMAT, Inc. Techniques for forming optoelectronic devices
KR20150056316A (ko) * 2013-11-15 2015-05-26 삼성디스플레이 주식회사 소자 기판 제조 방법 및 상기 방법을 이용하여 제조한 표시 장치
US9577110B2 (en) 2013-12-27 2017-02-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including an oxide semiconductor and the display device including the semiconductor device
US10224233B2 (en) 2014-11-18 2019-03-05 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation
CN117198983A (zh) * 2015-11-20 2023-12-08 环球晶圆股份有限公司 使半导体表面平整的制造方法
JP7034186B2 (ja) * 2017-07-14 2022-03-11 サンエディソン・セミコンダクター・リミテッド 絶縁体上半導体構造の製造方法
WO2020092570A1 (en) 2018-10-30 2020-05-07 North Carolina State University Torque density and efficiency improvement in ac machines
US11527701B2 (en) * 2019-10-28 2022-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Piezoelectric device and method of forming the same
CN112885713A (zh) * 2021-01-29 2021-06-01 合肥维信诺科技有限公司 改善膜质的方法和显示面板

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KR100232886B1 (ko) * 1996-11-23 1999-12-01 김영환 Soi 웨이퍼 제조방법
JPH1197379A (ja) * 1997-07-25 1999-04-09 Denso Corp 半導体基板及び半導体基板の製造方法
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
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JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
CN1118087C (zh) * 1999-09-27 2003-08-13 中国科学院半导体研究所 一种制备半导体衬底的方法
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US6583440B2 (en) 2000-11-30 2003-06-24 Seiko Epson Corporation Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
JP4507395B2 (ja) 2000-11-30 2010-07-21 セイコーエプソン株式会社 電気光学装置用素子基板の製造方法
US6376336B1 (en) * 2001-02-01 2002-04-23 Advanced Micro Devices, Inc. Frontside SOI gettering with phosphorus doping
DE10124030A1 (de) * 2001-05-16 2002-11-21 Atmel Germany Gmbh Verfahren zur Herstellung eines Silizium-Wafers
US7420147B2 (en) * 2001-09-12 2008-09-02 Reveo, Inc. Microchannel plate and method of manufacturing microchannel plate
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
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KR20060118437A (ko) * 2003-09-26 2006-11-23 위니베르시트카솔리끄드루뱅 저항손을 감소시키는 다층 반도체 구조의 제조 방법
FR2871172B1 (fr) * 2004-06-03 2006-09-22 Soitec Silicon On Insulator Support d'epitaxie hybride et son procede de fabrication
KR100634528B1 (ko) * 2004-12-03 2006-10-16 삼성전자주식회사 단결정 실리콘 필름의 제조방법
JP5128761B2 (ja) * 2005-05-19 2013-01-23 信越化学工業株式会社 Ｓｏｉウエーハの製造方法
US20070111468A1 (en) * 2005-07-19 2007-05-17 The Regents Of The University Of California Method for fabricating dislocation-free stressed thin films
US7268051B2 (en) 2005-08-26 2007-09-11 Corning Incorporated Semiconductor on glass insulator with deposited barrier layer
KR20080086899A (ko) 2005-12-27 2008-09-26 신에쓰 가가꾸 고교 가부시끼가이샤 Ｓｏｉ 웨이퍼의 제조 방법 및 ｓｏｉ 웨이퍼
JP2008004821A (ja) * 2006-06-23 2008-01-10 Sumco Corp 貼り合わせウェーハの製造方法
KR20100065145A (ko) * 2007-09-14 2010-06-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 전자 기기
JP2009135430A (ja) * 2007-10-10 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US7696058B2 (en) * 2007-10-31 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate

Also Published As

Publication number Publication date
KR20090045130A (ko) 2009-05-07
JP2009135465A (ja) 2009-06-18
US9837300B2 (en) 2017-12-05
CN101425454B (zh) 2014-11-05
US20090111236A1 (en) 2009-04-30
TWI470735B (zh) 2015-01-21
US8207045B2 (en) 2012-06-26
KR101497353B1 (ko) 2015-03-02
US7696058B2 (en) 2010-04-13
TW200943477A (en) 2009-10-16
US20120282757A1 (en) 2012-11-08
CN101425454A (zh) 2009-05-06
US20100120225A1 (en) 2010-05-13

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