KR101497353B1 - Ｓｏｉ 기판의 제작 방법 - Google Patents

Ｓｏｉ 기판의 제작 방법 Download PDF

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Publication number
KR101497353B1
KR101497353B1 KR1020080108090A KR20080108090A KR101497353B1 KR 101497353 B1 KR101497353 B1 KR 101497353B1 KR 1020080108090 A KR1020080108090 A KR 1020080108090A KR 20080108090 A KR20080108090 A KR 20080108090A KR 101497353 B1 KR101497353 B1 KR 101497353B1
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South Korea
Prior art keywords
substrate
layer
oxide film
semiconductor substrate
nitrogen
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Expired - Fee Related
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KR1020080108090A
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English (en)
Korean (ko)
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KR20090045130A (ko
Inventor
테츠야 카케하타
카주타카 쿠리키
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가부시키가이샤 한도오따이 에네루기 켄큐쇼
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Publication of KR20090045130A publication Critical patent/KR20090045130A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
KR1020080108090A 2007-10-31 2008-10-31 Ｓｏｉ 기판의 제작 방법 Expired - Fee Related KR101497353B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007283669 2007-10-31
JPJP-P-2007-283669 2007-10-31

Publications (2)

Publication Number Publication Date
KR20090045130A KR20090045130A (ko) 2009-05-07
KR101497353B1 true KR101497353B1 (ko) 2015-03-02

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Family Applications (1)

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KR1020080108090A Expired - Fee Related KR101497353B1 (ko) 2007-10-31 2008-10-31 Ｓｏｉ 기판의 제작 방법

Country Status (5)

Country Link
US (3) US7696058B2 (enExample)
JP (1) JP5542256B2 (enExample)
KR (1) KR101497353B1 (enExample)
CN (1) CN101425454B (enExample)
TW (1) TWI470735B (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7883990B2 (en) * 2007-10-31 2011-02-08 International Business Machines Corporation High resistivity SOI base wafer using thermally annealed substrate
US7696058B2 (en) * 2007-10-31 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP2009141093A (ja) 2007-12-06 2009-06-25 Toshiba Corp 発光素子及び発光素子の製造方法
JP5548395B2 (ja) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5663150B2 (ja) * 2008-07-22 2015-02-04 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
KR20120059509A (ko) * 2009-08-25 2012-06-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
JP2011077504A (ja) * 2009-09-02 2011-04-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US8655138B2 (en) 2010-05-10 2014-02-18 Cornell University Waveguide structure and related fabrication method
JP5917036B2 (ja) 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US9269582B2 (en) * 2011-03-24 2016-02-23 Entegris, Inc. Cluster ion implantation of arsenic and phosphorus
FR2975222A1 (fr) * 2011-05-10 2012-11-16 Soitec Silicon On Insulator Procede de fabrication d'un substrat semiconducteur
JP6016532B2 (ja) 2011-09-07 2016-10-26 株式会社半導体エネルギー研究所 半導体装置
US8575666B2 (en) * 2011-09-30 2013-11-05 Raytheon Company Method and structure having monolithic heterogeneous integration of compound semiconductors with elemental semiconductor
WO2014113503A1 (en) * 2013-01-16 2014-07-24 QMAT, Inc. Techniques for forming optoelectronic devices
KR20150056316A (ko) * 2013-11-15 2015-05-26 삼성디스플레이 주식회사 소자 기판 제조 방법 및 상기 방법을 이용하여 제조한 표시 장치
US9577110B2 (en) 2013-12-27 2017-02-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including an oxide semiconductor and the display device including the semiconductor device
WO2016081367A1 (en) 2014-11-18 2016-05-26 Sunedison Semiconductor Limited HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION
JP6749394B2 (ja) * 2015-11-20 2020-09-02 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 滑らかな半導体表面の製造方法
EP3993018B1 (en) * 2017-07-14 2024-09-11 Sunedison Semiconductor Limited Method of manufacture of a semiconductor on insulator structure
WO2020092570A1 (en) 2018-10-30 2020-05-07 North Carolina State University Torque density and efficiency improvement in ac machines
US11527701B2 (en) * 2019-10-28 2022-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Piezoelectric device and method of forming the same
CN112885713A (zh) * 2021-01-29 2021-06-01 合肥维信诺科技有限公司 改善膜质的方法和显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JPH1197379A (ja) * 1997-07-25 1999-04-09 Denso Corp 半導体基板及び半導体基板の製造方法
JP2002026007A (ja) * 2000-07-10 2002-01-25 Matsushita Electric Ind Co Ltd 薄膜構造体の形成方法、及び薄膜構造体の応力調整方法
WO2007024549A2 (en) * 2005-08-26 2007-03-01 Corning Incorporated Semiconductor on glass insulator with deposited barrier layer

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100232886B1 (ko) * 1996-11-23 1999-12-01 김영환 Soi 웨이퍼 제조방법
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
CN1118087C (zh) * 1999-09-27 2003-08-13 中国科学院半导体研究所 一种制备半导体衬底的方法
WO2001048825A1 (en) * 1999-12-24 2001-07-05 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer
US6900113B2 (en) * 2000-05-30 2005-05-31 Shin-Etsu Handotai Co., Ltd. Method for producing bonded wafer and bonded wafer
JP4507395B2 (ja) 2000-11-30 2010-07-21 セイコーエプソン株式会社 電気光学装置用素子基板の製造方法
US6583440B2 (en) 2000-11-30 2003-06-24 Seiko Epson Corporation Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
US6376336B1 (en) * 2001-02-01 2002-04-23 Advanced Micro Devices, Inc. Frontside SOI gettering with phosphorus doping
DE10124030A1 (de) * 2001-05-16 2002-11-21 Atmel Germany Gmbh Verfahren zur Herstellung eines Silizium-Wafers
US7420147B2 (en) * 2001-09-12 2008-09-02 Reveo, Inc. Microchannel plate and method of manufacturing microchannel plate
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US7713838B2 (en) * 2003-09-08 2010-05-11 Sumco Corporation SOI wafer and its manufacturing method
US20070032040A1 (en) * 2003-09-26 2007-02-08 Dimitri Lederer Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses
FR2871172B1 (fr) * 2004-06-03 2006-09-22 Soitec Silicon On Insulator Support d'epitaxie hybride et son procede de fabrication
KR100634528B1 (ko) * 2004-12-03 2006-10-16 삼성전자주식회사 단결정 실리콘 필름의 제조방법
JP5128761B2 (ja) * 2005-05-19 2013-01-23 信越化学工業株式会社 Ｓｏｉウエーハの製造方法
US20070111468A1 (en) * 2005-07-19 2007-05-17 The Regents Of The University Of California Method for fabricating dislocation-free stressed thin films
KR20080086899A (ko) 2005-12-27 2008-09-26 신에쓰 가가꾸 고교 가부시끼가이샤 Ｓｏｉ 웨이퍼의 제조 방법 및 ｓｏｉ 웨이퍼
JP2008004821A (ja) * 2006-06-23 2008-01-10 Sumco Corp 貼り合わせウェーハの製造方法
CN102646698B (zh) * 2007-09-14 2015-09-16 株式会社半导体能源研究所 半导体装置及电子设备
JP2009135430A (ja) * 2007-10-10 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US7696058B2 (en) * 2007-10-31 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0254532A (ja) * 1988-08-17 1990-02-23 Sony Corp Ｓｏｉ基板の製造方法
JPH1197379A (ja) * 1997-07-25 1999-04-09 Denso Corp 半導体基板及び半導体基板の製造方法
JP2002026007A (ja) * 2000-07-10 2002-01-25 Matsushita Electric Ind Co Ltd 薄膜構造体の形成方法、及び薄膜構造体の応力調整方法
WO2007024549A2 (en) * 2005-08-26 2007-03-01 Corning Incorporated Semiconductor on glass insulator with deposited barrier layer

Also Published As

Publication number Publication date
US7696058B2 (en) 2010-04-13
TW200943477A (en) 2009-10-16
US20120282757A1 (en) 2012-11-08
KR20090045130A (ko) 2009-05-07
JP5542256B2 (ja) 2014-07-09
US9837300B2 (en) 2017-12-05
CN101425454B (zh) 2014-11-05
CN101425454A (zh) 2009-05-06
US8207045B2 (en) 2012-06-26
US20100120225A1 (en) 2010-05-13
US20090111236A1 (en) 2009-04-30
TWI470735B (zh) 2015-01-21
JP2009135465A (ja) 2009-06-18

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