JP5548395B2 - Soi基板の作製方法 - Google Patents
Soi基板の作製方法 Download PDFInfo
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- JP5548395B2 JP5548395B2 JP2009139952A JP2009139952A JP5548395B2 JP 5548395 B2 JP5548395 B2 JP 5548395B2 JP 2009139952 A JP2009139952 A JP 2009139952A JP 2009139952 A JP2009139952 A JP 2009139952A JP 5548395 B2 JP5548395 B2 JP 5548395B2
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- oxide film
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Images
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- Microelectronics & Electronic Packaging (AREA)
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- Thin Film Transistor (AREA)
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Description
本実施の形態では、絶縁膜を介して半導体層が設けられた基板(例えば、SOI基板)を作製する方法に関して図面を参照して説明する。
O2+hν(λ1nm)→O(3P)+O(3P) ・・・ (1)
O(3P)+O2→O3 ・・・ (2)
O3+hν(λ2nm)→O(1D)+O2 ・・・ (3)
O2+hν(λ3nm)→O(1D)+O(3P) ・・・ (4)
O(3P)+O2→O3 ・・・ (5)
O3+hν(λ3nm)→O(1D)+O2 ・・・ (6)
本実施の形態では、上記実施の形態と異なるSOI基板の作製方法に関して図面を参照して説明する。具体的には、ベース基板上に窒素含有層を形成する前に、当該ベース基板にプラズマ処理を行う場合について説明する。
本実施の形態では、上記実施の形態と異なるSOI基板の作製方法に関して図面を参照して説明する。具体的には、1枚のベース基板に複数の半導体基板を貼り合わせる場合に関して説明する。
本実施の形態では、上記実施の形態で作製したSOI基板を用いて、半導体装置を作製する方法を説明する。
102 酸化膜
103 イオン
104 脆化領域
120 ベース基板
121 窒素含有層
124 単結晶半導体層
191 電極
192 電極
193 コンデンサ
195 ステージ
196 支持台
197 電極
198 電極
251 半導体層
252 半導体層
254 絶縁膜
255 ゲート電極
256 ゲート電極
257 低濃度不純物領域
258 チャネル形成領域
259 高濃度不純物領域
260 チャネル形成領域
261 サイドウォール絶縁膜
265 レジスト
267 高濃度不純物領域
268 絶縁膜
269 層間絶縁膜
270 配線
320 単結晶半導体層
322 走査線
323 信号線
324 画素電極
325 TFT
327 層間絶縁膜
328 電極
329 柱状スペーサ
330 配向膜
332 対向基板
333 対向電極
334 配向膜
335 液晶層
340 チャネル形成領域
341 高濃度不純物領域
401 選択用トランジスタ
402 表示制御用トランジスタ
403 半導体層
404 半導体層
405 走査線
406 信号線
407 電流供給線
408 画素電極
411 電極
412 ゲート電極
413 電極
427 層間絶縁膜
428 隔壁層
429 EL層
430 対向電極
431 対向基板
432 樹脂層
451 チャネル形成領域
452 高濃度不純物領域
500 マイクロプロセッサ
501 演算回路
502 演算回路制御部
503 命令解析部
504 制御部
505 タイミング制御部
506 レジスタ
507 レジスタ制御部
508 バスインターフェース
509 専用メモリ
510 メモリインターフェース
511 RFCPU
512 アナログ回路部
513 デジタル回路部
514 共振回路
515 整流回路
516 定電圧回路
517 リセット回路
518 発振回路
519 復調回路
520 変調回路
521 RFインターフェース
522 制御レジスタ
523 クロックコントローラ
524 インターフェース
525 中央処理ユニット
526 ランダムアクセスメモリ
527 専用メモリ
528 アンテナ
529 容量部
530 電源管理回路
701 筐体
702 筐体
703 表示部
704 スピーカ
705 マイクロフォン
706 操作キー
707 ポインティングデバイス
708 表面カメラ用レンズ
709 外部接続端子ジャック
710 イヤホン端子
711 キーボード
712 外部メモリスロット
713 裏面カメラ
714 ライト
Claims (2)
- 半導体基板上に酸化膜を形成し、前記酸化膜を介して前記半導体基板に加速されたイオンを照射することにより、前記半導体基板の表面から離れた領域に脆化領域を形成する工程と、
ベース基板上に、表面の平均粗さが0.5nm以下である窒素含有層を形成する工程と、
前記窒素含有層に対してプラズマ処理を行い、前記窒素含有層のSiN、SiN 3 を減少させ、SiOxを増加させる工程と、
前記酸化膜の表面と前記窒素含有層の表面とを接合させる工程と、
熱処理を行い、前記脆化領域において、前記半導体基板を分離することにより、前記ベース基板上に前記酸化膜及び前記窒素含有層を介して半導体層を形成する工程と、
を有するSOI基板の作製方法。 - 半導体基板上に酸化膜を形成し、前記酸化膜を介して前記半導体基板に加速されたイオンを照射することにより、前記半導体基板の表面から離れた領域に脆化領域を形成する工程と、
プラズマCVD法を用いて、基板温度を室温以上350℃以下として、ベース基板上に窒素含有層を形成する工程と、
前記窒素含有層に対してプラズマ処理を行い、前記窒素含有層のSiN、SiN 3 を減少させ、SiOxを増加させる工程と、
前記酸化膜の表面と前記窒素含有層の表面とを接合させる工程と、
熱処理を行い、前記脆化領域において、前記半導体基板を分離することにより、前記ベース基板上に前記酸化膜及び前記窒素含有層を介して半導体層を形成する工程と、
を有するSOI基板の作製方法。
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US7829432B2 (en) | 2010-11-09 |
TWI538111B (zh) | 2016-06-11 |
US20090325363A1 (en) | 2009-12-31 |
WO2009157369A1 (en) | 2009-12-30 |
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