JP5479446B2 - 窒化物および炭化シリコンをベースとする集積デバイス、および窒化物をベースとする集積デバイスを製造する方法 - Google Patents
窒化物および炭化シリコンをベースとする集積デバイス、および窒化物をベースとする集積デバイスを製造する方法 Download PDFInfo
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
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- H03H9/02—Details
- H03H9/02228—Guided bulk acoustic wave devices or Lamb wave devices having interdigital transducers situated in parallel planes on either side of a piezoelectric layer
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- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/0538—Constructional combinations of supports or holders with electromechanical or other electronic elements
- H03H9/0542—Constructional combinations of supports or holders with electromechanical or other electronic elements consisting of a lateral arrangement
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- H10N39/00—Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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Description
本願は2003年3月3日に出願された米国特許出願第10/378,331号、および2006年4月25日に出願された米国特許出願第11/410,768号の一部継続出願として、米国特許法第120条に基づく優先権を主張するものであり、これら米国特許出願の開示全体が本願に記載されているものとして、本明細書でこれら米国特許出願を参考例として援用する。
Claims (37)
- 共通する窒化物エピタキシャル層と、
前記共通する窒化物エピタキシャル層上に第1の少なくとも1つのイオン注入されたnタイプの領域を含む、前記共通する窒化物エピタキシャル層に設けられた第1タイプの窒化物デバイスとを備え、前記第1の少なくとも1つのイオン注入されたnタイプの領域は、前記共通する窒化物エピタキシャル層のドーピング濃度よりも高い第1のドーピング濃度を有し、
前記共通する窒化物エピタキシャル層上に第2の少なくとも1つのイオン注入されたnタイプの領域を含む、前記第1のタイプの窒化物デバイスと異なる第2のタイプの窒化物デバイスを備え、前記第2の少なくとも1つのイオン注入されたnタイプの領域は、前記少なくとも1つのイオン注入されたnタイプの第1の領域と異なり、前記共通する窒化物エピタキシャル層のドーピング濃度よりも高い第2のドーピング濃度を有し、
前記第1の少なくとも1つのイオン注入されたnタイプの領域に設けられ、前記第1のタイプの窒化物デバイスの第1の電子デバイスを構成する複数の第1の電気コンタクトと、
前記第2の少なくとも1つのイオン注入されたnタイプの領域に設けられ、前記第2のタイプの電子デバイスの第2の電子デバイスを構成する複数の第2の電気コンタクトとを備え、
前記共通する窒化物エピタキシャル層上の前記第2の少なくとも1つのイオン注入されたnタイプの領域は前記複数の第2の電気コンタクトの下側全体に延在する、モノリシック電子デバイス。 - 前記第1の少なくとも1つのイオン注入されたnタイプの領域は、前記第1の電子デバイスのためのソース領域およびドレイン領域を備え、前記第1の複数の電気コンタクトは、前記ソース領域のソースコンタクトと、前記ドレイン領域上のドレインコンタクトと、前記ソースコンタクトと前記ドレインコンタクトとの間のゲートコンタクトとを備え、
前記第2の少なくとも1つのイオン注入されたnタイプの領域は、高導電性のnタイプの領域を備え、前記第2の複数の電気コンタクトは、前記高導電性のnタイプ領域上に設けられたソースコンタクトと、ドレインコンタクトと、前記ソースコンタクトと前記ドレインコンタクトとの間のゲートコンタクトとを備える、請求項1に記載のモノリシック電子デバイス。 - 前記共通する窒化物エピタキシャル構造は、
窒化物チャンネル層と、
前記窒化物チャンネル層の上に設けられた窒化物バリア層とを備え、前記窒化物バリア層は、前記窒化物チャンネル層よりも高いバンドギャップを有し、
前記窒化物バリア層と前記窒化物チャンネルとは、前記窒化物チャンネル層と前記窒化物バリア層との間の境界部に二次元電子ガスを協働して誘導する、請求項2に記載のモノリシック電子デバイス。 - 前記バリア層上の高バンドギャップ層と、前記高バンドギャップ層上の窒化シリコン層とを更に含む、請求項3に記載のモノリシック電子デバイス。
- 前記高導電性のnタイプの領域は、前記高バンドギャップ層内にnタイプのAlxGa1−xN(0≦x≦1)のイオン注入された領域を備え、前記第2の電子デバイスは1×10 16 cm −3 未満のドーピング濃度を有する高導電性のnタイプの領域上に、nタイプのAlxGa1−xN(0≦x≦1)の層を備える、請求項4に記載のモノリシック電子デバイス。
- 前記第2電子デバイスのゲートコンタクトとドレインコンタクトとは、アノードを形成するように電気的に結合されている、請求項5に記載のモノリシックデバイス。
- 前記高導電性のnタイプの領域は5.0×10 18 〜6.0×10 18 cm−3のドーピング濃度および0.1〜1.0μmの深さを有する、請求項1に記載のモノリシックデバイス。
- 前記第1の電子デバイスは、高電子移動度トランジスタを備える、請求項1に記載のモノリシック電子デバイス。
- 前記第2の電子デバイスは、表面音響波デバイスを備える、請求項8に記載のモノリシック電子デバイス。
- 前記第2の電子デバイスは、ダイオードを備える、請求項8に記載のモノリシック電子デバイス。
- 前記第2の電子デバイスは、電界効果トランジスタを備える、請求項8に記載のモノリシック電子デバイス。
- 前記第2の電子デバイスは、MISHFETを備える、請求項8に記載のモノリシック電子デバイス。
- 窒化物チャンネル層と、
前記窒化物チャンネル層の上に設けられ、前記窒化物チャンネル層よりも高いバンドギャップを有する窒化物バリア層とを備え、
前記窒化物バリア層と前記窒化物チャンネル層とは、前記窒化物チャンネル層と前記窒化物バリア層との間の境界部に二次元電子ガスを協働して誘導し、
更にソース領域およびドレイン領域をそれぞれ構成する前記バリア層上に設けられた第1および第2のnタイプのイオン注入された領域と、
前記ソース領域と前記ドレイン領域との間に設けられ、第1トランジスタデバイスを構成する第1ゲート電極と、
前記バリア層上に設けられ、イオン注入された高導電性のnタイプ領域を構成する第3のnタイプのイオン注入された領域と、
前記イオン注入された高導電性のnタイプ領域上に設けられ、第2のトランジスタデバイスを構成する第2ゲート電極とを備え、
前記イオン注入された高導電性のnタイプの領域は、前記第2のトランジスタデバイスの下側全体に延在する、窒化物エピタキシャル構造を含むモノリシック電子デバイス。 - 共通する窒化物エピタキシャル層を形成するステップと、
前記共通する窒化物エピタキシャル層上に第1の少なくとも1つのイオン注入されたnタイプの領域を含む、前記共通する窒化物エピタキシャル層に設けられた第1タイプの窒化物デバイスを形成するステップとを備え、前記第1の少なくとも1つのイオン注入されたnタイプの領域は、前記共通する窒化物エピタキシャル層のドーピング濃度よりも高い第1のドーピング濃度を有し、
前記共通する窒化物エピタキシャル層上に第2の少なくとも1つのイオン注入されたnタイプの領域を含む、前記第1のタイプの窒化物デバイスと異なる第2のタイプの窒化物デバイスを形成するステップとを備え、前記第2の少なくとも1つのイオン注入されたnタイプの領域は、前記少なくとも1つのイオン注入されたnタイプの第1の領域と異なり、前記共通する窒化物エピタキシャル層のドーピング濃度よりも高い第2のドーピング濃度を有し、
前記第2の少なくとも1つのイオン注入されたnタイプの領域に設けられ、前記第1のタイプの電子デバイスの第1の電子デバイスを構成する複数の第1の電気コンタクトを形成するステップと、
前記第1の少なくとも1つのイオン注入されたnタイプの領域に設けられ、前記第2のタイプの窒化物デバイスの第2の電子デバイスを構成する複数の第2の電気コンタクトを形成するステップとを備え、
前記第2の複数の電気コンタクトを形成するステップは、前記第2の少なくとも1つのイオン注入されたnタイプの領域が前記第2の複数の電気コンタクトの下側全体に延在するように、当該第2の複数の電気コンタクトを前記第2の少なくとも1つのイオン注入されたnタイプの領域上に形成する、モノリシック電子デバイスを形成する方法。 - 前記第1の少なくとも1つのイオン注入されたnタイプ領域を形成するステップは、前記第1電子デバイスのためのソース領域およびドレイン領域にイオンを注入するステップを備え、前記第1の複数の電気コンタクトを形成するステップは、前記ソース領域上のソースコンタクト、前記ドレイン領域上のドレインコンタクトおよび前記ソースコンタクトと前記ドレインコンタクトとの間のゲートコンタクトを形成することを含み、
前記第2の少なくとも1つのイオン注入されたnタイプの領域を形成するステップは、高導電性のnタイプの領域にイオンを注入することを含み、前記第2の複数の電気接点を形成するステップは、前記高導電性nタイプの領域上でソースコンタクト、ドレインコンタクトおよび前記ソースコンタクトと前記ドレインコンタクトの間のゲートコンタクトを形成することを含む、請求項14に記載の方法。 - 前記高導電性のnタイプの領域を形成するステップは、5.0×10 18 〜6.0×10 18 cm−3のドーピング濃度および0.1〜1.0μmの深さを有する高導電性のnタイプの領域を形成することを含む、請求項14に記載の方法。
- 前記第2の電子デバイスのゲートコンタクトおよびドレインコンタクトを形成するステップは、前記ソースコンタクトと前記ドレインコンタクトとが電気的に結合されてカソードを形成するようにゲートコンタクトおよびドレインコンタクトを形成することを含む、請求項14に記載の方法。
- 前記共通する窒化物エピタキシャル構造を形成するステップは、
窒化物チャンネル層を形成するステップと、
前記窒化物チャンネル層の上に設けられた窒化物バリア層を形成するステップとを備え、前記窒化物バリア層は、前記窒化物チャンネル層よりも高いバンドギャップを有し、前記窒化物バリア層と前記窒化物チャンネルとは、前記窒化物チャンネル層と前記窒化物バリア層との間の境界部に二次元電子ガスを協働して誘導する、請求項15に記載の方法。 - 前記バリア層上に高バンドギャップ層と、前記高バンドギャップ層上の窒化シリコン層とを形成するステップを更に含む、請求項18に記載の方法。
- 前記高導電性のnタイプの領域を形成するステップは、前記高バンドギャップ層内にnタイプのAlxGa1−xN(0≦x≦1)の領域にイオン注入するステップを備え、1×10 16 cm−3未満のドーピング濃度を有する高導電性のnタイプの領域上に、nタイプのAlxGa1−xN(0≦x≦1)の層を形成するステップを備える、請求項19に記載の方法。
- 高いバンドギャップ層と、
前記高いバンドギャップ層の第1の部分上の第1のタイプの窒化物デバイスであって、当該第1のタイプの窒化物デバイスは前記第1のタイプの窒化物デバイスのソースおよびドレイン領域を各々規定する第1および第2のイオン注入領域を備え、
前記高いバンドギャップ層の第2の部分上で、前記第1のタイプの窒化物デバイスとは異なる第2のタイプの窒化物デバイスであって、当該第2のタイプの窒化物デバイスはイオン注入された高導電領域を備え、
前記第2のタイプの窒化物デバイスの前記イオン注入された高導電領域の少なくとも一部は、前記第1のタイプの窒化物デバイスの前記第1および第2のイオン注入領域の少なくとも一部と同一平面上にある、モノリシック電子デバイス。 - 前記第1および第2のイオン注入領域は第1および第2のイオン注入されたnタイプの領域であり、および
前記イオン注入された高導電領域はイオン注入された高導電nタイプの領域である、請求項21に記載のモノリシック電子デバイス。 - 前記第1および第2のイオン注入領域は前記高いバンドギャップ層の前記第1の部分に配置され、
前記イオン注入された高導電領域は前記高いバンドギャップ層の第2の部分に配置された、請求項21に記載のモノリシック電子デバイス。 - 前記高導電領域は5.0×10 18 〜6.0×10 18 cm −3 のドーピング濃度および0.1〜1.0μmの深さを有する、請求項21に記載のモノリシック電子デバイス。
- 前記第1および第2の領域は前記高いバンドギャップ層のドーピング濃度よりも大きな第1のドーピング濃度を有し、および
前記高導電領域は前記高いバンドギャップ層のドーピング濃度よりも大きな第2のドーピング濃度を有する、請求項21に記載のモノリシック電子デバイス。 - さらに、前記第1および第2のイオン注入領域上の第1の複数の電気コンタクトを備え、当該第1の複数の電気コンタクトは前記第1タイプの窒化物の第1電子デバイスを規定し、および
前記イオン注入された高導電イオン注入領域上の第2の複数の電気コンタクトであって、当該第2の複数の電気コンタクトは前記第2のタイプの電子デバイスの第2の電子デバイスを規定する、請求項21に記載のモノリシック電子デバイス。 - 前記高いバンドギャップ層上の上記イオン注入された高導電領域は、前記第2の複数の電気コンタクトの下側全体に延在する、請求項26に記載のモノリシック電子デバイス。
- さらに前記イオン注入された高導電領域上の再成長エピタキシャル層を備える、請求項21に記載のモノリシック電子デバイス。
- 前記再成長エピタキシャル層はnタイプ・ガリウム窒化物を含む、請求項28に記載のモノリシック電子デバイス。
- 高いバンドギャップ層と、
前記高いバンドギャップ層の第1の部分上の第1のタイプの窒化物デバイスであって、当該第1のタイプの窒化物デバイスは前記第1のタイプの窒化物デバイスのソースおよびドレイン領域を各々規定する第1および第2のイオン注入領域を備え、
前記第1および第2のイオン注入領域上の少なくとも第1および第2の電気コンタクトと、
前記高いバンドギャップ層の第2の部分上で、前記第1のタイプの窒化物デバイスとは異なる第2のタイプの窒化物デバイスであって、当該第2のタイプの窒化物デバイスはイオン注入された高導電領域を備え、
前記イオン注入高導電領域上の少なくとも第3の電気コンタクトと、
前記第1および第2イオン注入領域と前記第1および第2の電気コンタクト間の第1のインターフェースと、前記イオン注入された高導電領域と第3の電気コンタクトとの間の第2のインターフェースは同一平面上にある、モノリシック電子デバイス。 - 前記第1および第2のイオン注入領域は第1および第2のイオン注入nタイプの領域であり、および
前記イオン注入された高導電領域はイオン注入された高導電nタイプ領域である、請求項30に記載のモノリシック電子デバイス。 - 前記第1および第2のイオン注入領域は前記高いバンドギャップ層の前記第1の部分に配置され、
前記イオン注入された高導電領域は前記高いバンドギャップ層の第2の部分に配置された、請求項30に記載のモノリシック電子デバイス。 - 前記高導電領域は5.0×10 18 〜6.0×10 18 cm −3 のドーピング濃度および0.1〜1.0μmの深さを有する、請求項30に記載のモノリシック電子デバイス。
- 前記第1および第2のイオン注入された領域は前記高いバンドギャップ層のドーピング濃度よりも大きな第1のドーピング濃度を有し、および
前記イオン注入された高導電領域は前記高いバンドギャップ層のドーピング濃度よりも大きな第2のドーピング濃度を有する、請求項30に記載のモノリシック電子デバイス。 - 前記高いバンドギャップ層上のイオン注入された高導電領域は、前記第2の複数の電気コンタクトの下側全てに延在する、請求項30に記載のモノリシック電子デバイス。
- さらに、前記イオン注入された高導電領域上の再成長エピタキシャル層を含む、請求項30に記載のモノリシック電子デバイス。
- 前記再成長エピタキシャル層はnタイプ・ガリウム窒化物を含む請求項36に記載のモノリシック電子デバイス。
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CN101978489B (zh) | 2014-07-02 |
EP2495759B1 (en) | 2014-05-14 |
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