US20080197422A1 - Planar combined structure of a bipolar junction transistor and N-type/P-type metal semiconductor field-effect transistors and method for forming the same - Google Patents

Planar combined structure of a bipolar junction transistor and N-type/P-type metal semiconductor field-effect transistors and method for forming the same Download PDF

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US20080197422A1
US20080197422A1 US11/708,515 US70851507A US2008197422A1 US 20080197422 A1 US20080197422 A1 US 20080197422A1 US 70851507 A US70851507 A US 70851507A US 2008197422 A1 US2008197422 A1 US 2008197422A1
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Yue-Ming Hsin
Jinn-Kong Sheu
Kuang-Po Hsueh
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National Central University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to a technology of forming a bipolar junction transistor (BJT) and n-type/p-type metal-semiconductor field effect transistors (MESFETs) concurrently as a planar structure on the same gallium nitride (GaN) crystal growth layer.
  • BJT bipolar junction transistor
  • MESFETs n-type/p-type metal-semiconductor field effect transistors
  • a conventional planar structured gallium nitride (GaN) bipolar junction transistor comprises a semi-insulating substrate for crystal growth 107 , a collector layer 103 , a base layer 102 , a collector metal electrode 105 , a base metal electrode 106 , a GaN emitter region 101 and a collector contact well region 104 of an n-type GaN inverted from a p-type GaN formed by ion implantation or impurity diffusion technology.
  • the provision of the planar structure of the GaN BJT has the advantage that another device may be fabricated and thus combined with the GaN BJT on the same horizontal base. Meanwhile, the GaN material can be prevented from a high contact resistance of the base metal after a dry etching process is applied thereto.
  • the present invention discloses a new planar combined structure of the BJT and n-type/p-type MESFETs and a method for forming such planar combined structure.
  • the n-type GaN MESFET is formed at the same time when the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design.
  • the mask design it is possible to implant ions or diffuse impurity into a channel region of the n-type MESFET at the same time when ions are implanted or diffused with respect to an n-type inversion region of the GaN BJT, so that a p-type GaN inversion region of the MESFET is inverted into an n-type channel of the n-type MESFET.
  • the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET.
  • the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure. With this process performed, efficiency and cost for fabrication of the planar combined structure can be enhanced and lowered, respectively, which makes a significant improvement, compared with the prior art.
  • FIG. 1 is a cross sectional view of a conventional gallium nitride (GaN) bipolar junction transistor (BJT);
  • GaN gallium nitride
  • BJT bipolar junction transistor
  • FIG. 2 is a cross sectional view of a planar combined structure of a GaN BJT and a n-type/p-type metal semiconductor field effect transistor (MESFET);
  • MESFET metal semiconductor field effect transistor
  • FIG. 3A through 3H are cross sectional views of the planar combined structure shown in FIG. 2 formed at stages of a manufacturing process thereof for illustration of respective steps of the manufacturing process;
  • FIG. 4 is a flowchart for illustrating the manufacturing process corresponding to the structures shown in FIG. 3A through FIG. 3H .
  • an n-type channel region 201 b of an n-type metal semiconductor field effect transistor is formed concurrently when an emitter well region 201 a of a gallium nitride (GaN) bipolar junction transistor (BJT) is formed by means of a particular mask design.
  • the BJT and the n-type MESFET are intended to be formed on the same horizontal base.
  • a planar combined structure of this invention comprises a substrate 209 for crystal growth, an emitter well region 201 a, an n-type channel region 201 b of an n-type MESFET and a collector contact well region 202 of the GaN BJT.
  • a collector layer 203 a serves as a substrate layer 203 b of the n-type MESFET and also as a buried layer 203 c of the p-type MESFET.
  • a base layer 204 a of the GaN BJT serves as a buried layer 204 b of the n-type MESFET and also as a channel layer 204 c of the p-type MESFET.
  • a base metal electrode 205 a serves as a source metal electrode and a drain metal electrode 205 b of the p-type MESFET.
  • An emitter metal electrode and a collector metal electrode 206 a of the BJT are used concurrently as a source metal electrode and a drain metal electrode 206 b of the n-type MESFET, respectively.
  • a gate Schottky metal electrode 207 of the n-type MESFET and a gate Schottky metal electrode 208 of the p-type MESFET are formed separately.
  • the p-type MESFET is also intended to be formed on the same horizontal base with respect to the GaN BJT and the n-type MESFET.
  • the planar combined structure of the gallium nitride (GaN) bipolar junction transistor (BJT) and the n-type/p-type metal semiconductor field effect transistors (MESFETs) of the present invention comprises the following components: the substrate 209 for crystal growth, the GaN BJT, n-type MESFET formed on the substrate 209 for crystal growth and the p-type MESFET formed on the substrate 209 for crystal growth.
  • the GaN BJT comprises a low doped n-type collector layer 203 a formed on the substrate 209 for crystal growth; a high doped p-type base layer 204 a formed on the low doped collector layer 203 a; a high doped n-type emitter well region 201 a formed within the high doped p-type based layer 204 a; a high doped n-type collector contact well region 202 formed within the high doped p-type base layer 204 a; and an emitter metal electrode 206 a, a base metal electrode 205 a and a collector metal electrode 206 a formed on the emitter well region 201 a, the base layer 204 a and the collector contact well region 202 , respectively.
  • the n-type MESFET formed on the substrate 209 for crystal growth comprises a low doped n-type substrate layer 203 b formed on the substrate 209 for crystal growth; a high doped p-type buried layer 204 b formed on the low doped substrate layer 203 b; a high doped n-type channel region 201 b formed with the high doped p-type buried layer 204 b; and a gate Schottky metal electrode 207 , a drain metal electrode 206 b and a source metal 206 b formed on the high doped n-type channel region 210 b.
  • the p-type MESFET formed on the substrate 209 for crystal growth layer comprises a low doped n-type buried layer 203 c formed on the substrate 209 ; a high doped p-type channel layer 204 c formed on the low doped n-type buried layer 203 c; and a gate Schottky metal electrode 208 , a drain metal electrode 205 b and a source metal electrode 205 b formed on the high doped p-type channel layer 204 c.
  • the n-type layers 203 and p-type layer 204 are currently formed by a molecular beam epitaxy (MBE) method or a metal-organic vapor phase epitaxy (MOVPE) method, as shown in FIG. 3 .
  • MBE molecular beam epitaxy
  • MOVPE metal-organic vapor phase epitaxy
  • the substrate 209 for crystal growth is made of one selected from the group consisting of Al 2 O 3 , SiC, ZnO, Si, GaN, Al x Ga 1-x N, In x Ga 1-x N and In x Al y Ga 1-x-y N, wherein 0 ⁇ x ⁇ 1 and 0 ⁇ y ⁇ 1.
  • the substrate 209 is made of one selected from the group consisting of SiC, ZnO, GaN, Al x Ga 1-x N, In x Ga 1-x N and In x Al y Ga 1-x-y N, wherein 0 ⁇ x ⁇ 1 and 0 ⁇ y ⁇ 1.
  • each of the GaN BJT and n-type and p-type MESFETs is made of one selected from the group consisting of SiC, ZnO, GaN, Al x Ga 1-x N, In x Ga 1-x N and In x Al y Ga 1-x-y N, wherein 0 ⁇ x ⁇ 1 and 0 ⁇ y ⁇ 1.
  • each of the emitter, the collector contact well region 202 and the channel region 204 c is formed by the ion implantation method or the impurity diffusion method.
  • each of the emitter metal electrode 206 a, the base metal electrode 205 a, the collector metal electrode 206 a, the gate Schottky metal electrodes 207 , 208 , the source metal electrode and drain metal electrode 205 b is made of one selected from the group consisting of Au, Pt/Ti/Pt/Au, Ti/Al/Ti/Au, Ti/Au, Cr/Au, Pd/Au, Ti/Pd/Au, Pd/Ti/Au, Cr, Pt/Au, Ni/Au, Ta/Ti, Ti/Pt/Au, Ti/Cr/Au and Pt/Ru.
  • the GaN BJT and n-type/p-type MESFETs are formed on the substrate 209 concurrently.
  • FIG. 3 a through FIG. 3 h and FIG. 4 in which FIG. 3A through 3H are cross sectional views of the planar combined structure shown in FIG. 2 formed at stages of a manufacturing process thereof for illustration of respective steps of the manufacturing process, and FIG. 4 is a flowchart for illustrating the manufacturing process corresponding to the structures shown in FIG. 3A through FIG. 3H .
  • the method comprises the following steps.
  • the GaN crystal growth layer comprises a substrate 209 for crystal growth, an n-type layer 203 and a p-type layer 204 .
  • the n-type layer 203 comprises a collector layer 203 a, a substrate layer 203 b of the n-type MESFET and a buried layer 203 c of the p-type MESFET as shown in FIG. 3 b.
  • the p-type layer 204 comprises a base layer 204 a of the GaN BJT, a buried layer 204 b of the n-type MESFET and a channel layer 204 c of the p-type MESFET.
  • Step b forming a collector layer 203 a of the GaN BJT, a substrate layer 203 b of an n-type MESFET, a buried layer 203 c of a p-type MESFET, a base layer 204 a of the GaN BJT, a buried layer 204 b of the n-type MESFET and a channel layer 204 c of the p-type MESFET on the crystal growth substrate 209 (Step b).
  • Step c forming a collector contact well region 202 of the BJT by using the ion implantation or impurity diffusion method
  • Step d forming an emitter well region 201 a of the BJT and a channel region 201 b of the n-type MESFET concurrently by also using the ion implantation or impurity diffusion method
  • Step e forming a base metal electrode 205 a of the BJT and a drain metal electrode and a source metal electrode 205 b of the p-type MESFET concurrently.
  • Step f forming an emitter metal electrode and a collector metal electrode 206 a of the BJT and a drain metal electrode and a source metal electrode 206 b of the n-type MESFET concurrently.

Abstract

A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of Invention
  • The present invention relates to a technology of forming a bipolar junction transistor (BJT) and n-type/p-type metal-semiconductor field effect transistors (MESFETs) concurrently as a planar structure on the same gallium nitride (GaN) crystal growth layer.
  • 2. Related Art
  • As shown in FIG. 1, a conventional planar structured gallium nitride (GaN) bipolar junction transistor (BJT) comprises a semi-insulating substrate for crystal growth 107, a collector layer 103, a base layer 102, a collector metal electrode 105, a base metal electrode 106, a GaN emitter region 101 and a collector contact well region 104 of an n-type GaN inverted from a p-type GaN formed by ion implantation or impurity diffusion technology. Generally, the provision of the planar structure of the GaN BJT has the advantage that another device may be fabricated and thus combined with the GaN BJT on the same horizontal base. Meanwhile, the GaN material can be prevented from a high contact resistance of the base metal after a dry etching process is applied thereto.
    • SUMMARY OF THE INVENTION
  • In view of the disadvantages discussed above with respect to the conventional planar combined structure of the gallium nitride (GaN) bipolar junction transistor (BJT) and the n-type/p-type metal -semiconductor field effect transistors (MESFETs), where the BJT and n-type/p-type MESFETs are separately formed by using different processes, the present invention discloses a new planar combined structure of the BJT and n-type/p-type MESFETs and a method for forming such planar combined structure.
  • In accordance with the present invention, in the planar combined structure, the n-type GaN MESFET is formed at the same time when the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design. By means of the mask design, it is possible to implant ions or diffuse impurity into a channel region of the n-type MESFET at the same time when ions are implanted or diffused with respect to an n-type inversion region of the GaN BJT, so that a p-type GaN inversion region of the MESFET is inverted into an n-type channel of the n-type MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure. With this process performed, efficiency and cost for fabrication of the planar combined structure can be enhanced and lowered, respectively, which makes a significant improvement, compared with the prior art.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross sectional view of a conventional gallium nitride (GaN) bipolar junction transistor (BJT);
  • FIG. 2 is a cross sectional view of a planar combined structure of a GaN BJT and a n-type/p-type metal semiconductor field effect transistor (MESFET);
  • FIG. 3A through 3H are cross sectional views of the planar combined structure shown in FIG. 2 formed at stages of a manufacturing process thereof for illustration of respective steps of the manufacturing process; and
  • FIG. 4 is a flowchart for illustrating the manufacturing process corresponding to the structures shown in FIG. 3A through FIG. 3H.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • In accordance with the present invention, an n-type channel region 201 b of an n-type metal semiconductor field effect transistor (MESFET) is formed concurrently when an emitter well region 201 a of a gallium nitride (GaN) bipolar junction transistor (BJT) is formed by means of a particular mask design. And the BJT and the n-type MESFET are intended to be formed on the same horizontal base. As shown in FIG. 2, a planar combined structure of this invention comprises a substrate 209 for crystal growth, an emitter well region 201 a, an n-type channel region 201 b of an n-type MESFET and a collector contact well region 202 of the GaN BJT. A collector layer 203 a serves as a substrate layer 203 b of the n-type MESFET and also as a buried layer 203 c of the p-type MESFET. A base layer 204 a of the GaN BJT serves as a buried layer 204 b of the n-type MESFET and also as a channel layer 204 c of the p-type MESFET. A base metal electrode 205 a serves as a source metal electrode and a drain metal electrode 205 b of the p-type MESFET. An emitter metal electrode and a collector metal electrode 206 a of the BJT are used concurrently as a source metal electrode and a drain metal electrode 206 b of the n-type MESFET, respectively. A gate Schottky metal electrode 207 of the n-type MESFET and a gate Schottky metal electrode 208 of the p-type MESFET are formed separately. In the planar combined structure, the p-type MESFET is also intended to be formed on the same horizontal base with respect to the GaN BJT and the n-type MESFET.
  • Specifically, the planar combined structure of the gallium nitride (GaN) bipolar junction transistor (BJT) and the n-type/p-type metal semiconductor field effect transistors (MESFETs) of the present invention comprises the following components: the substrate 209 for crystal growth, the GaN BJT, n-type MESFET formed on the substrate 209 for crystal growth and the p-type MESFET formed on the substrate 209 for crystal growth.
  • The GaN BJT comprises a low doped n-type collector layer 203 a formed on the substrate 209 for crystal growth; a high doped p-type base layer 204 a formed on the low doped collector layer 203 a; a high doped n-type emitter well region 201 a formed within the high doped p-type based layer 204 a; a high doped n-type collector contact well region 202 formed within the high doped p-type base layer 204 a; and an emitter metal electrode 206 a, a base metal electrode 205 a and a collector metal electrode 206 a formed on the emitter well region 201 a, the base layer 204 a and the collector contact well region 202, respectively.
  • The n-type MESFET formed on the substrate 209 for crystal growth comprises a low doped n-type substrate layer 203 b formed on the substrate 209 for crystal growth; a high doped p-type buried layer 204 b formed on the low doped substrate layer 203 b; a high doped n-type channel region 201 b formed with the high doped p-type buried layer 204 b; and a gate Schottky metal electrode 207, a drain metal electrode 206 b and a source metal 206 b formed on the high doped n-type channel region 210 b.
  • The p-type MESFET formed on the substrate 209 for crystal growth layer comprises a low doped n-type buried layer 203 c formed on the substrate 209; a high doped p-type channel layer 204 c formed on the low doped n-type buried layer 203 c; and a gate Schottky metal electrode 208, a drain metal electrode 205 b and a source metal electrode 205 b formed on the high doped p-type channel layer 204 c.
  • In the planar combined structure, the n-type layers 203 and p-type layer 204 are currently formed by a molecular beam epitaxy (MBE) method or a metal-organic vapor phase epitaxy (MOVPE) method, as shown in FIG. 3.
  • In the planar combined structure, the substrate 209 for crystal growth is made of one selected from the group consisting of Al2O3, SiC, ZnO, Si, GaN, AlxGa1-xN, InxGa1-xN and InxAlyGa1-x-yN, wherein 0≦x≦1 and 0≦y≦1.
  • In the planar combined structure, the substrate 209 is made of one selected from the group consisting of SiC, ZnO, GaN, AlxGa1-xN, InxGa1-xN and InxAlyGa1-x-yN, wherein 0≦x≦1 and 0≦y≦1.
  • In the planar combined structure, each of the GaN BJT and n-type and p-type MESFETs is made of one selected from the group consisting of SiC, ZnO, GaN, AlxGa1-xN, InxGa1-xN and InxAlyGa1-x-yN, wherein 0≦x≦1 and 0≦y≦1.
  • In the planar combined structure, each of the emitter, the collector contact well region 202 and the channel region 204 c is formed by the ion implantation method or the impurity diffusion method.
  • In the planar combined structure, each of the emitter metal electrode 206 a, the base metal electrode 205 a, the collector metal electrode 206 a, the gate Schottky metal electrodes 207, 208, the source metal electrode and drain metal electrode 205 b is made of one selected from the group consisting of Au, Pt/Ti/Pt/Au, Ti/Al/Ti/Au, Ti/Au, Cr/Au, Pd/Au, Ti/Pd/Au, Pd/Ti/Au, Cr, Pt/Au, Ni/Au, Ta/Ti, Ti/Pt/Au, Ti/Cr/Au and Pt/Ru.
  • In the planar combined structure, the GaN BJT and n-type/p-type MESFETs are formed on the substrate 209 concurrently.
  • Herein below, a method for forming a planar combined structure of the gallium nitride (GaN) bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field effect transistors (MESFETs) according to the present invention will be described with reference FIG. 3 a through FIG. 3 h and FIG. 4, in which FIG. 3A through 3H are cross sectional views of the planar combined structure shown in FIG. 2 formed at stages of a manufacturing process thereof for illustration of respective steps of the manufacturing process, and FIG. 4 is a flowchart for illustrating the manufacturing process corresponding to the structures shown in FIG. 3A through FIG. 3H. The method comprises the following steps. At first, growing a GaN crystal growth layer having a p-n junction by forming a GaN substrate for crystal growth having an n-type layer and a p-type layer (Step a). The GaN crystal growth layer comprises a substrate 209 for crystal growth, an n-type layer 203 and a p-type layer 204. The n-type layer 203 comprises a collector layer 203 a, a substrate layer 203 b of the n-type MESFET and a buried layer 203 c of the p-type MESFET as shown in FIG. 3 b. The p-type layer 204 comprises a base layer 204 a of the GaN BJT, a buried layer 204 b of the n-type MESFET and a channel layer 204 c of the p-type MESFET.
  • Next, forming a collector layer 203 a of the GaN BJT, a substrate layer 203 b of an n-type MESFET, a buried layer 203 c of a p-type MESFET, a base layer 204 a of the GaN BJT, a buried layer 204 b of the n-type MESFET and a channel layer 204 c of the p-type MESFET on the crystal growth substrate 209 (Step b).
  • Then, forming a collector contact well region 202 of the BJT by using the ion implantation or impurity diffusion method (Step c). At the same time, forming an emitter well region 201 a of the BJT and a channel region 201 b of the n-type MESFET concurrently by also using the ion implantation or impurity diffusion method (Step d). Between Steps c and d, a step of activating the emitter contact well 201 a of the BJT and the channel region 201 b of the n-type MESFET concurrently by providing a high temperature may be provided. Thereafter, forming a base metal electrode 205 a of the BJT and a drain metal electrode and a source metal electrode 205 b of the p-type MESFET concurrently (Step e).
  • Then, forming an emitter metal electrode and a collector metal electrode 206 a of the BJT and a drain metal electrode and a source metal electrode 206 b of the n-type MESFET concurrently (Step f).
  • Then, forming a first gate Schottky metal electrode 207 on the n-type MESFET (Step g).
  • Finally, forming a second gate Schottky metal electrode 208 on the p-type MESFET (Step h).
  • As such, the formation of the planar combined structure of the BJT and n-type/p-type MESFETs is completed.

Claims (10)

1. A planar combined structure of a gallium nitride (GaN) bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field effect transistors (MESFETs), comprising:
(a) a substrate for crystal growth;
(b) the GaN BJT, comprising;
a low doped n-type collector layer formed on the substrate for crystal growth;
a high doped p-type base layer formed on the low doped collector layer;
a high doped n-type emitter well region formed within the high doped p-type based layer;
a high doped n-type collector contact well region formed within the high doped p-type base layer; and
an emitter metal electrode, a base metal electrode and a collector metal electrode formed on the emitter well region, the base layer and the collector contact well region, respectively;
(c) the n-type MESFET formed on the substrate for crystal growth, comprising:
a low doped n-type substrate layer formed on the substrate for crystal growth;
a high doped p-type buried layer formed on the low doped substrate layer;
a high doped n-type channel region formed with the high doped p-type buried layer; and
a gate Schottky metal electrode, a drain metal electrode and a source metal formed on the high doped n-type channel region; and
(d) a p-type MESFET formed on the crystal growth layer, comprising:
a low doped n-type buried layer formed on the substrate for crystal growth;
a high doped p-type channel layer formed on the low doped n-type buried layer; and
a gate Schottky metal electrode, a drain metal electrode and a source metal electrode formed on the high doped p-type channel layer.
2. The planar combined structure as claimed in claim 1, wherein each of the low doped n-type collector layer, the high doped p-type base layer, the high doped n-type emitter well region, the high doped n-type collector contact well region, the low doped n-type substrate layer, the high doped p-type buried layer, the high doped n-type channel region, the low doped n-type buried layer and the high doped p-type channel layer are concurrently formed by one of a molecular beam epitaxy (MBE) method and a metal-organic vapor phase epitaxy (MOVPE) methods.
3. The planar combined structure as claimed in claim 1, wherein the substrate for crystal growth is made of one selected from the group consisting of Al2O3, SiC, ZnO, Si, GaN, AlxGa1-xN, InxGa1-xN and InxAlyGa1-x-yN, wherein 0≦x≦1 and 0≦y≦1.
4. The planar combined structure as claimed in claim 1, wherein the crystal growth layer is made of one selected from the group consisting of SiC, ZnO, GaN, AlxGa1-xN, InxGa1-xN and InxAlyGa1-x-yN, wherein 0≦x≦1 and 0≦y≦1.
5. The planar combined structure as claimed in claim 1, wherein each of the GaN BJT and n-type and p-type MESFETs is made of one selected from the group consisting of SiC, ZnO, GaN, AlxGa1-xN, InxGa1-xN and InxAlyGa1-x-yN, wherein 0≦x≦1 and 0≦y≦1.
6. The planar combined structure as claimed in claim 1, wherein each of the emitter, the collector contact well region and the channel region is formed by one of an ion implantation method and an impurity diffusion method.
7. The planar combined structure as claimed in claim 1, wherein each of the emitter metal electrode, the base metal electrode, the collector metal electrode, the respective gate Schottky metal electrodes of the n-type and p-type MESFETS, the source metal electrode and drain metal electrode is made of one selected from the group consisting of Au, Pt/Ti/Pt/Au, Ti/Al/Ti/Au, Ti/Au, Cr/Au, Pd/Au, Ti/Pd/Au, Pd/Ti/Au, Cr, Pt/Au, Ni/Au, Ta/Ti, Ti/Pt/Au, Ti/Cr/Au and Pt/Ru.
8. The planar combined structure as claimed in claim 1, wherein the GaN BJT and n-type/p-type MESFETs are formed on the crystal growth layer concurrently.
9. A method for forming a planar combined structure of a gallium nitride (GaN) bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field effect transistors (MESFETs), comprising the steps of:
(a) growing a GaN crystal growth layer having a p-n junction by forming a GaN substrate for crystal growth having an n-type layer and a p-type layer;
(b) forming a collector layer of the GaN BJT, a substrate layer of an n-type MESFET, a buried layer of a p-type MESFET, a base layer of the GaN BJT, a buried layer of the n-type MESFET and a channel layer of the p-type MESFET;
(c) forming a collector well region of the BJT, and a collector well region of the BJT and a channel region of the n-type MESFET concurrently by using one of an ion implantation method and an impurity diffusion method;
(d) forming a base metal electrode of the BJT and a drain metal electrode and a source metal electrode of the p-type MESFET concurrently;
(e) forming an emitter metal electrode and a collector metal electrode of the BJT and a drain metal electrode and a source metal electrode of the n-type MESFET concurrently;
(f) forming a first gate Schottky metal electrode on the n-type MESFET; and
(g) forming a second gate Schottky metal electrode on the p-type MESFET.
10. The method as claimed in claim 9, further comprising a step, between the steps (c) and (d), of activating the collector contact well of the BJT and the emitter well region/channel region of the n-type MESFET concurrently or separately by providing a high temperature.
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