WO2022049983A1 - 半導体装置、半導体モジュール、及び無線通信装置 - Google Patents
半導体装置、半導体モジュール、及び無線通信装置 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Definitions
- This disclosure relates to semiconductor devices, semiconductor modules, and wireless communication devices.
- HEMTs high electron mobility transistors
- Nitride semiconductors have a larger bandgap and have a hexagonal-specific polarization as compared to Si, GaAs, and the like. Therefore, HEMTs using nitride semiconductors are expected as transistors capable of low resistance, high withstand voltage, and high-speed operation.
- HEMT is expected to be applied to power devices, RF (Radio Frequency) devices, and the like.
- RF Radio Frequency
- HEMT using AlGaN for the barrier layer has been put into practical use.
- a HEMT using AlInN for the barrier layer has been proposed (for example, Patent Document 1). Since a HEMT using AlInN for the barrier layer can obtain a higher two-dimensional electron gas concentration than a HEMT using AlGaN for the barrier layer, it is expected that the output can be further increased.
- AlInN has a lower crystal growth temperature than other nitride semiconductors such as AlGaN and GaN. Therefore, for example, when the n-type semiconductor layer is re-grown or ion-implanted in order to reduce the resistance between the source or drain electrode and the channel, AlInN is determined by the thermal history during these process steps. The crystal structure of the above may deteriorate. As a result, the sheet resistance of the HEMT channel may increase and the device characteristics may deteriorate. Therefore, in HEMT, it is desired to improve the heat resistance of the barrier layer containing AlInN.
- the semiconductor device includes a channel layer including a first nitride semiconductor and a second nitride semiconductor having a bandgap larger than that of the first nitride semiconductor, and is provided on the channel layer.
- the semiconductor module includes a channel layer including a first nitride semiconductor and a second nitride semiconductor having a bandgap larger than that of the first nitride semiconductor, and is provided on the channel layer.
- the semiconductor device includes a layer and a barrier layer including Al x2 In (1-x2) N (0 ⁇ x2 ⁇ 1) and provided on the intermediate layer.
- the wireless communication device includes a channel layer including a first nitride semiconductor and a second nitride semiconductor having a bandgap larger than that of the first nitride semiconductor, and is provided on the channel layer. It contains the spacer layer and Al x1 In y1 Ga (1-x1-y1) N (0 ⁇ x1 ⁇ 1,0 ⁇ y1 ⁇ 1,0 ⁇ x1 + y1 ⁇ 1), and is provided on the spacer layer.
- a semiconductor device including an intermediate layer and a barrier layer including Al x2 In (1-x2) N (0 ⁇ x2 ⁇ 1) and provided on the intermediate layer is provided.
- the channel layer containing the first nitride semiconductor and the spacer containing the second nitride semiconductor having a bandgap larger than that of the first nitride semiconductor.
- Layers, intermediate layers containing AlInGaN, and barriers containing AlInN are sequentially laminated.
- the semiconductor device can suppress the diffusion of the alloy between the channel layer and the barrier layer by the heat treatment.
- FIG. 1 is a vertical sectional view showing the configuration of the semiconductor device 100 according to the present embodiment.
- the semiconductor device 100 includes a substrate 110, a first buffer layer 111, a second buffer layer 113, a channel layer 115, a spacer layer 121, an intermediate layer 123, and a barrier layer 131. It includes a regrowth layer 141, a source electrode 143S, a drain electrode 143D, a gate insulating film 151, and a gate electrode 153.
- the semiconductor device 100 is a high electron mobility transistor (HEMT) having a two-dimensional electron gas layer (2DEG) as a channel generated by the difference between the magnitude of polarization of the channel layer 115 and the magnitude of polarization of the barrier layer 131. ).
- the two-dimensional electron gas layer (2DEG) is generated, for example, at the interface of the channel layer 115 on the barrier layer 131 side.
- the substrate 110 is a support for the semiconductor device 100.
- the substrate 110 may be a SiC substrate, a sapphire substrate, a Si substrate, or the like. Since the semiconductor device 100 is provided with the first buffer layer 111 and the second buffer layer 113 that alleviate the mismatch of the lattice constants between the substrate 110 and the channel layer 115, the substrate 110 is made of a material having a lattice constant different from that of the channel layer 115. It may be a substrate composed of.
- the substrate 110 may be a substrate made of a semiconductor material having a lattice constant close to that of the nitride semiconductor constituting the channel layer 115.
- the substrate 110 may be a substrate made of a III-V compound semiconductor such as GaN or AlN.
- the semiconductor device 100 can more easily form the channel layer 115 obtained by epitaxially growing the nitride semiconductor.
- the first buffer layer 111 and the second buffer layer 113 are made of an epitaxially grown nitride semiconductor and are provided on the substrate 110.
- the first buffer layer 111 and the second buffer layer 113 can alleviate the lattice mismatch between the substrate 110 and the channel layer 115 by controlling the lattice constant of the surface on which the channel layer 115 is provided. According to this, the first buffer layer 111 and the second buffer layer 113 can improve the crystal state of the channel layer 115 and suppress the warp of the substrate 110.
- the first buffer layer 111 is made of AlN and the second buffer layer 113 is AlGaN. It may be composed of. However, depending on the configuration of the substrate 110 and the channel layer 115, the first buffer layer 111 and the second buffer layer 113 may not be provided, or only the first buffer layer 111 may be provided.
- the channel layer 115 is made of a nitride semiconductor having a bandgap smaller than that of the spacer layer 121 and the barrier layer 131, and is provided on the second buffer layer 113.
- the channel layer 115 can accumulate carriers at the interface on the barrier layer 131 side due to the difference in the magnitude of polarization from the barrier layer 131.
- the channel layer 115 is composed of epitaxially grown Al x4 In y4 Ga (1-x4-y4) N (0 ⁇ x4 ⁇ 1,0 ⁇ y4 ⁇ 1,0 ⁇ x4 + y4 ⁇ 1). good.
- the channel layer 115 may be composed of epitaxially grown GaN, InGaN, InN, AlGaN, or AlInGaN. More specifically, the channel layer 115 may be composed of undoped u-GaN to which impurities are not added. In such a case, the channel layer 115 can suppress the scattering of impurities of the carriers, so that the mobility of the carriers can be further increased.
- the spacer layer 121 is made of a nitride semiconductor having a bandgap larger than that of the channel layer 115, and is provided on the channel layer 115.
- the spacer layer 121 can reduce alloy scattering between the barrier layer 131 and the channel layer 115, and can suppress the decrease in carrier mobility of the two-dimensional electron gas layer (2DEG) due to alloy scattering.
- the spacer layer 121 is composed of epitaxially grown Al x3 In y3 Ga (1-x3-y3) N (0 ⁇ x3 ⁇ 1,0 ⁇ y3 ⁇ 1,0 ⁇ x3 + y3 ⁇ 1). good.
- the spacer layer 121 may be made of AlN, or may be made of AlGaN or AlInGaN.
- the thickness of the spacer layer 121 is preferably 0.5 nm or more and 3 nm or less, for example.
- the spacer layer 121 can form a layer more easily.
- the spacer layer 121 can more appropriately control the bandgap profile of the semiconductor device 100, which will be described later, so that the two-dimensional electron gas generated in the channel layer 115 can be controlled more appropriately.
- the carrier density of the layer (2DEG) can be further increased.
- the intermediate layer 123 is composed of epitaxially grown Al x1 In y1 Ga (1-x1-y1) N (0 ⁇ x1 ⁇ 1,0 ⁇ y1 ⁇ 1,0 ⁇ x1 + y1 ⁇ 1) on the spacer layer 121. It will be provided. Since Al x1 In y1 Ga (1-x1-y1) N constituting the intermediate layer 123 is a quaternary nitride semiconductor, it is simpler than Al x2 In (1-x2) N constituting the barrier layer 131. It is easy to obtain mixed crystals with excellent crystallinity.
- the intermediate layer 123 can further clarify the interface between the barrier layer 131 and the spacer layer 121 and suppress the disturbance of the interface due to heat, so that the layer structure of the channel layer 115 and the barrier layer 131 due to heat can be suppressed. Deterioration can be suppressed.
- the Ga composition (1-x1-y1) of Al x1 In y1 Ga (1-x1-y1) N constituting the intermediate layer 123 is preferably 0.01 or more and 0.3 or less.
- the Ga composition (1-x1-y1) of the intermediate layer 123 is 0.01 or more and 0.3 or less, the crystallinity of the intermediate layer 123 is further improved and the disturbance of the interface due to heat can be suppressed. It is possible to suppress deterioration of the layer structure of the channel layer 115 and the barrier layer 131 due to heat.
- the thickness of the intermediate layer 123 is preferably 0.5 nm or more and 10 nm or less.
- the intermediate layer 123 can form a layer more easily.
- the intermediate layer 123 can more appropriately control the bandgap profile of the semiconductor device 100, which will be described later, so that the two-dimensional electron gas generated in the channel layer 115 can be controlled more appropriately.
- the carrier density of the layer (2DEG) can be further increased.
- the thickness of the intermediate layer 123 is more preferably 1.0 nm or more and 5.0 nm or less.
- the barrier layer 131 is made of a nitride semiconductor having a bandgap larger than that of the channel layer 115, and is provided on the intermediate layer 123.
- the barrier layer 131 can accumulate carriers in the channel layer 115 on the barrier layer 131 side by spontaneous polarization or piezo polarization.
- a two-dimensional electron gas layer (2DEG) having high mobility and high carrier concentration can be formed in the channel layer 115 on the barrier layer 131 side.
- the barrier layer 131 is composed of epitaxially grown Al x2 In (1-x2) N (where 0 ⁇ x2 ⁇ 1).
- the barrier layer 131 may be composed of undoped u-Al x2 In (1-x2) N to which impurities are not added. In such a case, the barrier layer 131 can suppress the scattering of impurities of carriers in the channel layer 115, so that the mobility of carriers can be further increased.
- the carrier density of the two-dimensional electron gas layer (2DEG) can be controlled by, for example, the bandgap profile of each layer from the barrier layer 131 to the channel layer 115.
- the control of the carrier density of the two-dimensional electron gas layer (2DEG) will be described with reference to FIGS. 2 and 3.
- FIG. 2 is a graph showing a band lineup of a conduction band minimum of a laminated body in which a channel layer 115, a spacer layer 121, and a barrier layer 131 are laminated.
- FIG. 3 is a graph showing the band lineup of the conduction band minimum of the laminated body in which the channel layer 115, the spacer layer 121, the intermediate layer 123, and the barrier layer 131 are laminated.
- the height of the conduction band minimum of the barrier layer 131 is one factor that determines the carrier density of the two-dimensional electron gas layer (2DEG).
- the higher the Al composition of each layer the greater the polarization of each layer, and therefore the greater the inclination of the conduction band minimum.
- the thicker the thickness of each layer the higher the height of the conduction band minimum. Therefore, by appropriately controlling the thickness and composition of each layer from the barrier layer 131 to the channel layer 115 and controlling the height of the conduction band minimum of the barrier layer 131, the carrier density of the two-dimensional electron gas layer (2DEG) is controlled. Can be enhanced.
- the barrier layer 131 is preferably composed of Al x2 In (1-x2) N, which has a higher proportion of Al composition than Al x1 In y1 Ga (1-x1-y1) N constituting the intermediate layer 123. .. That is, since the barrier layer 131 is composed of a nitride semiconductor such that x1 ⁇ x2 with respect to the intermediate layer 123, a larger polarization can be obtained, so that the carrier of the two-dimensional electron gas layer (2DEG) can be obtained. The concentration can be increased.
- the barrier layer 131 is composed of a nitride semiconductor having x2 of more than 0.7, a larger polarization can be obtained, so that the carrier concentration of the two-dimensional electron gas layer (2DEG) is further increased. be able to.
- the barrier layer 131 and the intermediate layer 123 are composed of a nitride semiconductor having x1 ⁇ x2 and y1 ⁇ (1-x2). In such a case, since the barrier layer 131 and the intermediate layer 123 can further increase the polarization of the barrier layer 131, the carrier concentration of the two-dimensional electron gas layer (2DEG) can be further increased.
- the thickness of the barrier layer is preferably 4 nm or more and 20 nm or less.
- the barrier layer 131 can more appropriately control the bandgap profile of the semiconductor device 100, so that the carrier density of the two-dimensional electron gas layer (2DEG) generated in the channel layer 115 can be further increased. ..
- the thickness of the barrier layer is more preferably 8 nm or more and 15 nm or less.
- the regrowth layer 141 is composed of a nitride semiconductor containing an n-type impurity, and is provided on the barrier layer 131, the intermediate layer 123, the spacer layer 121, and the channel layer 115 on both sides of the gate electrode 153. Specifically, the regrowth layer 141 is provided by embedding a pair of recesses dug from the barrier layer 131 to the channel layer 115 with an n-type nitride semiconductor. For example, the regrowth layer 141 is provided by selectively epitaxially growing a nitride semiconductor containing an n-type impurity in the recesses provided in the regions corresponding to the source electrode 143S and the drain electrode 143D using a selection mask. May be good.
- the regrowth layer 141 has higher conductivity than the barrier layer 131, the source electrode 143S and the drain electrode 143D provided on the regrowth layer 141 and the two-dimensional electron gas layer (2DEG) are electrically connected with low resistance. Can be connected.
- the regrowth layer may be composed of GaN containing n-type impurities such as Si or Ge at 1.0 ⁇ 10 19 pieces / cm 3 or more.
- the regrowth layer 141 may be composed of AlInGaN containing an n-type impurity, which easily grows at a lower temperature than GaN.
- the source electrode 143S and the drain electrode 143D are made of a conductive material and are provided on the regrowth layer 141 provided on both sides of the gate electrode 153.
- the source electrode 143S and the drain electrode 143D can be electrically connected to the two-dimensional electron gas layer (2DEG) generated in the channel layer 115 via the regrowth layer 141.
- the source electrode 143S and the drain electrode 143D may be provided in a structure in which Ti (titanium), Al (aluminum), Ni (nickel), and Au (gold) are sequentially laminated from the regrowth layer 141 side.
- the gate insulating film 151 is made of an insulating material and is provided on the barrier layer 131. Specifically, the gate insulating film 151 is provided with a material having an insulating property with respect to the barrier layer 131 and the gate electrode 153. According to this, the gate insulating film 151 protects the surface of the barrier layer 131 from impurities such as ions and improves the surface of the barrier layer 131, thereby suppressing deterioration of the characteristics of the semiconductor device 100. ..
- the gate insulating film 151 may be provided as a single-layer film or a laminated film with Al 2 O 3 or HfO 2 having a film thickness of about 10 nm.
- the gate electrode 153 is made of a conductive material and is provided on the gate insulating film 151.
- the gate electrode 153 is provided between the source electrode 143S and the drain electrode 143D, and together with the gate insulating film 151, constitutes a MIS (Metal-Insulator-Semiconductor) gate.
- the gate electrode 153 may be provided by laminating Ni (nickel) and Au (gold) from the gate insulating film 151 side.
- the gate electrode 153 can control the carrier concentration of the two-dimensional electron gas layer (2DEG) formed on the channel layer 115 by the applied voltage. Specifically, the gate electrode 153 controls the thickness of the depletion layer formed in the lower barrier layer 131 by the applied voltage, so that the carrier concentration of the two-dimensional electron gas layer (2DEG) generated in the channel layer 115 is changed into an electric field. It can be controlled by the effect.
- the semiconductor device 100 according to the present embodiment can suppress the disturbance of the interface between the channel layer 115 and the barrier layer 131 due to heat, the layers of the channel layer 115 and the barrier layer 131 due to heat can be suppressed. Deterioration of the structure can be suppressed. Therefore, according to the technique according to the present disclosure, the heat resistance of the semiconductor device 100 can be improved.
- the semiconductor device 100 since the semiconductor device 100 according to the present embodiment can perform crystal growth at a higher temperature when the regrowth layer 141 is formed, the crystallinity of the regrowth layer 141 can be improved. Therefore, the semiconductor device 100 can reduce the contact resistance between the source electrode 143S and the drain electrode 143D and the two-dimensional electron gas layer (2DEG), and can improve the output efficiency.
- the semiconductor device 100 can reduce the contact resistance between the source electrode 143S and the drain electrode 143D and the two-dimensional electron gas layer (2DEG), and can improve the output efficiency.
- the semiconductor device 100 can suppress the deterioration of the sheet resistance of the two-dimensional electron gas layer (2DEG) at the time of forming the regrowth layer 141, so that the output efficiency can be improved.
- 2DEG two-dimensional electron gas layer
- MOCVD MetalOrganic Chemical Vapor Deposition
- H2, N2 , or NH3 the semiconductor device 100 can clean the regrowth surface by controlling the gas atmosphere of the regrowth layer 141 before regrowth with H2, N2 , or NH3 . Therefore, the semiconductor device 100 can reduce the contact resistance and carrier trap at the interface of the regrowth layer 141.
- FIGS. 4 to 9. 4 to 9 are vertical cross-sectional views showing each process of the manufacturing method of the semiconductor device 100 according to the present embodiment.
- the first buffer layer 111, the second buffer layer 113, the channel layer 115, the spacer layer 121, the intermediate layer 123, and the barrier layer 131 are sequentially epitaxially grown on the substrate 110.
- the substrate 110 a Si substrate, a sapphire substrate, a SiC substrate, a GaN substrate, an AlN substrate, a GaAs substrate, a ZnO substrate, a ScAlMgO substrate, or the like can be used. Give an explanation.
- a Si substrate having a (111) plane as a main surface is introduced into a MOCVD apparatus, thermal cleaning is performed at 1000 ° C. for about 10 minutes, and then AlN is epitaxially grown at about 700 ° C. to 1100 ° C. at 100 nm to 300 nm.
- the second buffer layer 113 is formed by epitaxially growing AlGaN having an Al composition of about 0.20 on the first buffer layer 111 at 100 nm to 500 nm at about 900 ° C to 1100 ° C.
- the channel layer 115 is formed by epitaxially growing GaN on the second buffer layer 113 at about 900 ° C. to 1100 ° C. at 500 nm to 2000 nm.
- the spacer layer 121 is formed by epitaxially growing AlN on the channel layer 115 at 900 ° C to 1100 ° C at about 0.5 nm to 5 nm.
- the intermediate layer 123 is formed by epitaxially growing AlInGaN on the spacer layer 121 at 700 ° C. to 900 ° C. at about 0.5 nm to 5 nm.
- the barrier layer 131 is formed by epitaxially growing AlInN on the intermediate layer 123 at 700 ° C. to 900 ° C. at about 5 nm to 20 nm.
- the gate insulating film 151 is formed by forming a film of SiN, SiO 2 , or Al2O 3 on the barrier layer 131. Subsequently, the gate insulating film 151 is wet-etched using a resist patterned so as to open the region corresponding to the source electrode 143S and the drain electrode 143D, and the gate insulation of the region corresponding to the source electrode 143S and the drain electrode 143D is performed. The film 151 is removed.
- the barrier layer 131, the intermediate layer 123, the spacer layer 121, and the channel layer 115 in the region corresponding to the source electrode 143S and the drain electrode 143D are removed by dry etching to obtain about 100 nm. It forms a depth opening 141H.
- the re-growth layer 141 is formed by selectively growing n-type GaN in the opening 141H by using MOCVD, MBE (Molecular Beam Epitaxy), or sputtering. At this time, for example, Si or Ge can be used as the n-type impurity.
- the source electrode 143S and the drain electrode 143D are formed by sequentially laminating Ti, Al, Ni, and Au on the regrowth layer 141.
- the gate electrode 153 is formed by sequentially laminating Ni and Au on the gate insulating film 151 between the source electrode 143S and the drain electrode 143D.
- the semiconductor device 100 according to the present embodiment can be formed.
- FIGS. 10 to 13 show only the configuration above the second buffer layer 113.
- the configuration of the second buffer layer 113 and below is substantially the same as that of the semiconductor device 100 shown in FIG.
- FIG. 10 is a vertical sectional view showing the configuration of the semiconductor device 100A according to the first modification.
- the semiconductor device 100A according to the first modification is different from the semiconductor device 100 shown in FIG. 1 in that the composition of AlInGaN constituting the intermediate layer 123A fluctuates in the stacking direction of the semiconductor device 100A.
- the intermediate layer 123A in the direction from the spacer layer 121 side to the barrier layer 131 side, Al x1 In y1 Ga (1-x1-y1) N (0 ⁇ x1 ⁇ 1,0 ⁇ y1 ⁇ 1, It may be provided so that the ratio (1-x1-y1) of the Ga composition of 0 ⁇ x1 + y1 ⁇ 1) decreases stepwise or continuously. That is, the intermediate layer 123A may be provided so that the ratio of Ga composition decreases toward the crystal growth direction. According to this, since the intermediate layer 123A can alleviate the composition difference of the nitride semiconductors constituting the spacer layer 121 and the barrier layer 131, each layer can be more easily epitaxially grown.
- FIG. 11 is a vertical sectional view showing the configuration of the semiconductor device 100B according to the second modification.
- the semiconductor device 100B according to the second modification is different from the semiconductor device 100 shown in FIG. 1 in that a graded layer 125 is further provided between the intermediate layer 123 and the barrier layer 131.
- the graded layer 125 is provided between the intermediate layer 123 and the barrier layer 131, and the proportion of Ga composition gradually or continuously decreases in the direction from the intermediate layer 123 side to the barrier layer 131 side. It may be composed of AlInGaN.
- the thickness of the graded layer 125 may be, for example, 0.5 nm or more and 5 nm or less. According to this, since the graded layer 125 can alleviate the composition difference of the nitride semiconductors constituting the intermediate layer 123 and the barrier layer 131, each layer can be more easily epitaxially grown.
- FIG. 11 shows an example in which the graded layer 125 is provided between the intermediate layer 123 and the barrier layer 131, but this modification is not limited to such an example.
- the graded layer 125 may be provided between the spacer layer 121 and the intermediate layer 123. Even in such a case, the graded layer 125 can alleviate the composition difference of the nitride semiconductors constituting the spacer layer 121 and the intermediate layer 123, so that each layer can be more easily epitaxially grown.
- FIG. 12 is a vertical sectional view showing the configuration of the semiconductor device 100C according to the third modification.
- the semiconductor device 100C according to the third modification is different from the semiconductor device 100 shown in FIG. 1 in that the protective layer 133 is provided on the barrier layer 131.
- the protective layer 133 is composed of AlInGaN and is provided on the barrier layer 131.
- the thickness of the protective layer 133 may be, for example, 0.5 nm or more and 5 nm or less. According to this, since the protective layer 133 can protect the barrier layer 131 from the film forming process of the gate insulating film 151 and the like, it suppresses the deterioration of the crystallinity of the barrier layer 131 after the formation of the barrier layer 131. be able to.
- FIG. 13 is a vertical sectional view showing the configuration of the semiconductor device 100D according to the fourth modification.
- the semiconductor device 100D according to the fourth modification is different from the semiconductor device 100 shown in FIG. 1 in that the channel layer 115 is composed of the upper channel layer 115B and the lower channel layer 115A.
- the lower channel layer 115A may be made of, for example, GaN.
- the upper channel layer 115B may be composed of, for example, AlGaN, InGaN, or AlInGaN.
- the upper channel layer 115B a two-dimensional electron gas layer (2DEG) is generated by the difference in the magnitude of polarization from the spacer layer 121, the intermediate layer 123, and the barrier layer 131 provided on the upper channel layer 115B. Therefore, the upper channel layer 115B is composed of a nitride semiconductor having a bandgap smaller than that of the spacer layer 121, the intermediate layer 123, and the barrier layer 131.
- the lower channel layer 115A since the lower channel layer 115A does not contribute to the formation of the two-dimensional electron gas layer (2DEG), it is made of a nitride semiconductor in consideration of the ease of epitaxial growth without considering the size of the band gap.
- the semiconductor device 100D can obtain the same effect as the semiconductor device 100 shown in FIG.
- FIG. 14 is a schematic perspective view showing the configuration of the semiconductor module 1.
- the semiconductor module 1 includes, for example, a plurality of edge antennas 20 formed in an array and front-end components such as a switch 10, a low noise amplifier 41, a bandpass filter 42, and a power amplifier 43. Is an antenna-integrated module mounted as a module on one chip 50.
- the semiconductor module 1 can be used, for example, as a transceiver for wireless communication.
- the semiconductor module 1 includes, for example, the semiconductor device 100 according to the present embodiment as a transistor constituting a switch 10, a low noise amplifier 41, a power amplifier 43, or the like.
- the semiconductor module 1 using radio waves in a higher frequency band, the propagation loss of radio waves becomes larger. Therefore, it is desired that the semiconductor module 1 compatible with 5G transmit radio waves with higher power. Since the semiconductor module 1 including the semiconductor device 100 according to the present embodiment can improve the device characteristics, it is possible to perform high output, low power consumption, and high reliability wireless communication. That is, the semiconductor module 1 can be more preferably used for the 5th generation mobile communication (5G).
- FIG. 15 is a block diagram showing the configuration of the wireless communication device 2.
- the wireless communication device 2 includes an antenna ANT, an antenna switch circuit 3, a high power amplifier HPA, a high frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a base band unit BB, and an audio output unit. It includes a MIC, a data output unit DT, and an interface unit I / F (for example, wireless LAN (Wireless Local Area Network: W-LAN), Bluetooth (registered trademark), etc.).
- the wireless communication device 2 is a mobile phone system having multiple functions such as voice, data communication, and LAN connection.
- a transmission signal is output from the baseband portion BB to the antenna ANT via the high frequency integrated circuit RFIC, the high power amplifier HPA, and the antenna switch circuit 3 at the time of transmission. Further, in the wireless communication device 2, the received signal is input from the antenna ANT to the baseband portion BB via the antenna switch circuit 3 and the high frequency integrated circuit RFIC at the time of reception.
- the received signal processed by the baseband unit BB is output to the outside of the wireless communication device 2 from, for example, the voice output unit MIC, the data output unit DT, or the interface unit I / F.
- the wireless communication device 2 includes the semiconductor device 100 according to the present embodiment as a transistor constituting the antenna switch circuit 3, the high power amplifier HPA, the high frequency integrated circuit RFIC, the baseband portion BB, and the like. According to this, since the wireless communication device 2 can further improve the device characteristics, it is possible to perform high output, low power consumption, and highly reliable wireless communication.
- Barrier layers made of Al 0.81 In 0.19 N having a film thickness of 9 nm were sequentially laminated to prepare a laminated body according to an example.
- the sheet resistance of the two-dimensional electron gas layer generated in the channel layer of the laminated body according to the examples and the comparative examples was measured by the eddy current method.
- the sheet resistance of the two-dimensional electron gas layer was measured at four points immediately after the formation of the laminate, after the heat treatment at 800 ° C. for 3 minutes, after the heat treatment at 850 ° C. for 3 minutes, or after the heat treatment at 900 ° C. for 3 minutes. The measurement results are shown in the scatter plot of FIG.
- the measurement result immediately after the formation of the laminate is “as green”
- the measurement result after the heat treatment at 800 ° C. for 3 minutes is “800 ° C.”
- the measurement result after the heat treatment at 850 ° C. for 3 minutes is “850 ° C.”.
- the measurement result after the heat treatment at 900 ° C. for 3 minutes is shown at "900 ° C.”.
- the laminate according to the example can suppress an increase in the sheet resistance of the two-dimensional electron gas layer due to the heat treatment at 850 ° C. or higher with respect to the laminate according to the comparative example. can.
- the sheet resistance is increased by about 1.5 times by the heat treatment at 850 ° C. for 3 minutes, and the sheet resistance is increased by about 4 times by the heat treatment at 900 ° C. for 3 minutes. It will increase.
- the sheet resistance is only increased by about 1.2 times even after the heat treatment at 900 ° C. for 3 minutes.
- the laminated body according to the example has improved heat resistance as compared with the laminated body according to the comparative example.
- the laminate according to the embodiment can suppress the sheet resistance of the two-dimensional electron gas layer to 280 ⁇ / ⁇ or less even after the heat treatment at 850 ° C. for 3 minutes.
- the crystallinity of the regrowth layer can be improved because the heat treatment at 850 ° C. for 3 minutes can be performed by using the laminate according to the embodiment. .. Therefore, the semiconductor device according to the present embodiment can suppress the sheet resistance of the two-dimensional electron gas layer to 280 ⁇ / ⁇ or less, and reduce the contact resistance between the source electrode and the drain electrode and the two-dimensional electron gas layer. Therefore, the output efficiency can be improved.
- the technology according to the present disclosure may have the following configuration.
- the semiconductor device according to the present embodiment can suppress the alloy diffusion between the channel layer and the barrier layer due to the heat treatment, so that the heat treatment is performed at a higher temperature. Even in this case, it is possible to suppress an increase in the sheet resistance of the two-dimensional electron gas layer. Therefore, the semiconductor device according to the present embodiment can improve the heat resistance.
- the effects exerted by the techniques according to the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described in the present disclosure.
- the Al x1 In y1 Ga (1-x1-y1) N contained in the intermediate layer is any one of the above (1) to (5), wherein the ratio of Ga decreases from the spacer layer toward the barrier layer.
- the second nitride semiconductor is Al x3 In y3 Ga (1-x3-y3) N (0 ⁇ x3 ⁇ 1,0 ⁇ y3 ⁇ 1,0 ⁇ x3 + y3 ⁇ 1), and the above (1) to (6). ).
- the first nitride semiconductor is Al x4 In y4 Ga (1-x4-y4) N (0 ⁇ x4 ⁇ 1,0 ⁇ y4 ⁇ 1,0 ⁇ x4 + y4 ⁇ 1). ).
- the semiconductor device according to any one of the items.
- a source electrode provided on one of the regrowth layers and The semiconductor device according to any one of (1) to (9) above, further comprising a drain electrode provided on the other side of the regrowth layer.
- the semiconductor device according to any one of (1) to (10) above, further comprising a gate electrode provided on the barrier layer via a gate insulating film.
- a two-dimensional electron gas layer is generated in the channel layer, and a two-dimensional electron gas layer is generated.
- the semiconductor device according to any one of (1) to (11) above, wherein the sheet resistance of the two-dimensional electron gas layer is 280 ⁇ / ⁇ or less.
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Abstract
Description
1.半導体装置の構成
2.半導体装置の製造方法
3.変形例
4.適用例
4.1.半導体モジュール
4.2.無線通信装置
まず、図1を参照して、本開示の一実施形態に係る半導体装置の構成について説明する。図1は、本実施形態に係る半導体装置100の構成を示す縦断面図である。
対応する領域に設けられた凹部にn型不純物を含む窒化物半導体を選択的にエピタキシャル成長させることで設けられてもよい。
上させることができる。
次に、図4~図9を参照して、本実施形態に係る半導体装置100の製造方法の一例について説明する。図4~図9は、本実施形態に係る半導体装置100の製造方法の各工程を示す縦断面図である。
続いて、図10~図13を参照して、本実施形態に係る半導体装置100の第1~第4の変形例について説明する。なお、図10~図13では、第2バッファ層113より上の構成についてのみ示す。第1~第4の変形例に係る半導体装置では、第2バッファ層113以下の構成は、図1で示した半導体装置100と実質的に同様である。
図10は、第1の変形例に係る半導体装置100Aの構成を示す縦断面図である。第1の変形例に係る半導体装置100Aは、中間層123Aを構成するAlInGaNの組成が半導体装置100Aの積層方向に変動する点が図1で示した半導体装置100と異なる。
図11は、第2の変形例に係る半導体装置100Bの構成を示す縦断面図である。第2の変形例に係る半導体装置100Bは、中間層123とバリア層131との間にグレーデッド層125がさらに設けられている点が図1で示した半導体装置100と異なる。
図12は、第3の変形例に係る半導体装置100Cの構成を示す縦断面図である。第3の変形例に係る半導体装置100Cは、バリア層131の上に保護層133が設けられている点が図1で示した半導体装置100と異なる。
図13は、第4の変形例に係る半導体装置100Dの構成を示す縦断面図である。第4の変形例に係る半導体装置100Dは、チャネル層115が上部チャネル層115B及び下部チャネル層115Aで構成されている点が図1で示した半導体装置100と異なる。
(4.1.半導体モジュール)
続いて、図14を参照して、本開示に係る技術の第1の適用例である半導体モジュールについて説明する。図14は、半導体モジュール1の構成を示す模式的な斜視図である。
次に、図15を参照して、本開示に係る技術の第2の適用例である無線通信装置について説明する。図15は、無線通信装置2の構成を示すブロック図である。
GaNからなるチャネル層の上に、膜厚1nmのAl0.9Ga0.1Nからなるスペーサ層、膜厚1nmのAl0.8In0.1Ga0.1Nからなる中間層、及び膜厚9nmのAl0.81In0.19Nからなるバリア層を順次積層し、実施例に係る積層体を作製した。
GaNからなるチャネル層の上に、膜厚1nmのAl0.9Ga0.1Nからなるスペーサ層、及び膜厚9nmのAl0.81In0.19Nからなるバリア層を順次積層し、比較例に係る積層体を作製した。
実施例及び比較例に係る積層体のチャネル層に生成される二次元電子ガス層のシート抵抗を渦電流法によって測定した。二次元電子ガス層のシート抵抗の測定は、積層体の形成直後、800℃3分間の熱処理後、850℃3分間の熱処理後、又は900℃3分間の熱処理後の4点で行った。測定結果を図16の散布図に示す。
(1)
第1窒化物半導体を含むチャネル層と、
前記第1窒化物半導体よりバンドギャップが大きい第2窒化物半導体を含み、前記チャネル層の上に設けられたスペーサ層と、
Alx1Iny1Ga(1-x1-y1)N(0<x1<1,0<y1<1,0<x1+y1<1)を含み、前記スペーサ層の上に設けられた中間層と、
Alx2In(1-x2)N(0<x2<1)を含み、前記中間層の上に設けられたバリア層と
を備える、半導体装置。
(2)
前記x1、前記x2、及び前記y1は、x1<x2、及びy1<(1-x2)の関係式を満たす、上記(1)に記載の半導体装置。
(3)
前記x2は、0.7超である、上記(1)又は(2)に記載の半導体装置。
(4)
前記中間層の厚みは、0.5nm以上10nm以下である、上記(1)~(3)のいずれか一項に記載の半導体装置。
(5)
前記バリア層の厚みは、4nm以上20nm以下である、上記(1)~(4)のいずれか一項に記載の半導体装置。
(6)
前記中間層に含まれる前記Alx1Iny1Ga(1-x1-y1)Nは、前記スペーサ層から前記バリア層に向かってGaの割合が低下する、上記(1)~(5)のいずれか一項に記載の半導体装置。
(7)
前記第2窒化物半導体は、Alx3Iny3Ga(1-x3-y3)N(0<x3<1,0≦y3<1,0<x3+y3<1)である、上記(1)~(6)のいずれか一項に記載の半導体装置。
(8)
前記スペーサ層の厚みは、0.5nm以上3nm以下である、上記(1)~(7)のいずれか一項に記載の半導体装置。
(9)
前記第1窒化物半導体は、Alx4Iny4Ga(1-x4-y4)N(0≦x4≦1,0≦y4≦1,0≦x4+y4≦1)である、上記(1)~(8)のいずれか一項に記載の半導体装置。
(10)
n型のAlInGaNを含み、前記バリア層から前記スペーサ層まで掘り込まれた一対の凹部にそれぞれ設けられた再成長層と、
前記再成長層の一方の上に設けられたソース電極と、
前記再成長層の他方の上に設けられたドレイン電極と
をさらに備える、上記(1)~(9)のいずれか一項に記載の半導体装置。
(11)
前記バリア層の上にゲート絶縁膜を介して設けられたゲート電極をさらに備える、上記(1)~(10)のいずれか一項に記載の半導体装置。
(12)
前記チャネル層には、2次元電子ガス層が生成され、
前記2次元電子ガス層のシート抵抗は、280Ω/□以下である、上記(1)~(11)のいずれか一項に記載の半導体装置。
(13)
第1窒化物半導体を含むチャネル層と、
前記第1窒化物半導体よりバンドギャップが大きい第2窒化物半導体を含み、前記チャネル層の上に設けられたスペーサ層と、
Alx1Iny1Ga(1-x1-y1)N(0<x1<1,0<y1<1,0<x1+y1<1)を含み、前記スペーサ層の上に設けられた中間層と、
Alx2In(1-x2)N(0<x2<1)を含み、前記中間層の上に設けられたバリア層と
を含む半導体装置
を備える、半導体モジュール。
(14)
第1窒化物半導体を含むチャネル層と、
前記第1窒化物半導体よりバンドギャップが大きい第2窒化物半導体を含み、前記チャネル層の上に設けられたスペーサ層と、
Alx1Iny1Ga(1-x1-y1)N(0<x1<1,0<y1<1,0<x1+y1<1)を含み、前記スペーサ層の上に設けられた中間層と、
Alx2In(1-x2)N(0<x2<1)を含み、前記中間層の上に設けられたバリア層と
を含む半導体装置
を備える、無線通信装置。
Claims (14)
- 第1窒化物半導体を含むチャネル層と、
前記第1窒化物半導体よりバンドギャップが大きい第2窒化物半導体を含み、前記チャネル層の上に設けられたスペーサ層と、
Alx1Iny1Ga(1-x1-y1)N(0<x1<1,0<y1<1,0<x1+y1<1)を含み、前記スペーサ層の上に設けられた中間層と、
Alx2In(1-x2)N(0<x2<1)を含み、前記中間層の上に設けられたバリア層と
を備える、半導体装置。 - 前記x1、前記x2、及び前記y1は、x1<x2、及びy1<(1-x2)の関係式を満たす、請求項1に記載の半導体装置。
- 前記x2は、0.7超である、請求項1に記載の半導体装置。
- 前記中間層の厚みは、0.5nm以上10nm以下である、請求項1に記載の半導体装置。
- 前記バリア層の厚みは、4nm以上20nm以下である、請求項1に記載の半導体装置。
- 前記中間層に含まれる前記Alx1Iny1Ga(1-x1-y1)Nは、前記スペーサ層から前記バリア層に向かってGaの割合が低下する、請求項1に記載の半導体装置。
- 前記第2窒化物半導体は、Alx3Iny3Ga(1-x3-y3)N(0<x3<1,0≦y3<1,0<x3+y3<1)である、請求項1に記載の半導体装置。
- 前記スペーサ層の厚みは、0.5nm以上3nm以下である、請求項1に記載の半導体装置。
- 前記第1窒化物半導体は、Alx4Iny4Ga(1-x4-y4)N(0≦x4≦1,0≦y4≦1,0≦x4+y4≦1)である、請求項1に記載の半導体装置。
- n型のAlInGaNを含み、前記バリア層から前記スペーサ層まで掘り込まれた一対の凹部にそれぞれ設けられた再成長層と、
前記再成長層の一方の上に設けられたソース電極と、
前記再成長層の他方の上に設けられたドレイン電極と
をさらに備える、請求項1に記載の半導体装置。 - 前記バリア層の上にゲート絶縁膜を介して設けられたゲート電極をさらに備える、請求項1に記載の半導体装置。
- 前記チャネル層には、2次元電子ガス層が生成され、
前記2次元電子ガス層のシート抵抗は、280Ω/□以下である、請求項1に記載の半導体装置。 - 第1窒化物半導体を含むチャネル層と、
前記第1窒化物半導体よりバンドギャップが大きい第2窒化物半導体を含み、前記チャネル層の上に設けられたスペーサ層と、
Alx1Iny1Ga(1-x1-y1)N(0<x1<1,0<y1<1,0<x1+y1<1)を含み、前記スペーサ層の上に設けられた中間層と、
Alx2In(1-x2)N(0<x2<1)を含み、前記中間層の上に設けられたバリア層と
を含む半導体装置
を備える、半導体モジュール。 - 第1窒化物半導体を含むチャネル層と、
前記第1窒化物半導体よりバンドギャップが大きい第2窒化物半導体を含み、前記チャネル層の上に設けられたスペーサ層と、
Alx1Iny1Ga(1-x1-y1)N(0<x1<1,0<y1<1,0<x1+y1<1)を含み、前記スペーサ層の上に設けられた中間層と、
Alx2In(1-x2)N(0<x2<1)を含み、前記中間層の上に設けられたバリア層と
を含む半導体装置
を備える、無線通信装置。
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WO2023228611A1 (ja) * | 2022-05-24 | 2023-11-30 | ソニーセミコンダクタソリューションズ株式会社 | 高電子移動度トランジスタ及び半導体装置 |
WO2024048266A1 (ja) * | 2022-09-01 | 2024-03-07 | ソニーグループ株式会社 | 半導体デバイス、半導体モジュールおよび無線通信装置 |
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JP2003197644A (ja) * | 2001-12-26 | 2003-07-11 | Matsushita Electric Ind Co Ltd | 通信機器用半導体装置 |
JP2005217364A (ja) * | 2004-02-02 | 2005-08-11 | Nippon Telegr & Teleph Corp <Ntt> | リセスゲート構造hfetおよびその製造方法 |
JP2015192004A (ja) * | 2014-03-28 | 2015-11-02 | 国立大学法人 名古屋工業大学 | ドレイン電流密度・相互コンダクタンスを大幅に改善したリセス構造のmis型ノーマリオフhemt素子 |
JP2016225578A (ja) * | 2015-06-03 | 2016-12-28 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
JP2018085414A (ja) * | 2016-11-22 | 2018-05-31 | 富士通株式会社 | 化合物半導体装置 |
WO2019208034A1 (ja) * | 2018-04-27 | 2019-10-31 | ソニーセミコンダクタソリューションズ株式会社 | スイッチングトランジスタ及び半導体モジュール |
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2021
- 2021-08-05 JP JP2022546184A patent/JPWO2022049983A1/ja active Pending
- 2021-08-05 WO PCT/JP2021/029047 patent/WO2022049983A1/ja active Application Filing
- 2021-08-05 US US18/041,870 patent/US20240030332A1/en active Pending
- 2021-08-05 CN CN202180051723.2A patent/CN116097409A/zh active Pending
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JP2003197644A (ja) * | 2001-12-26 | 2003-07-11 | Matsushita Electric Ind Co Ltd | 通信機器用半導体装置 |
JP2005217364A (ja) * | 2004-02-02 | 2005-08-11 | Nippon Telegr & Teleph Corp <Ntt> | リセスゲート構造hfetおよびその製造方法 |
JP2015192004A (ja) * | 2014-03-28 | 2015-11-02 | 国立大学法人 名古屋工業大学 | ドレイン電流密度・相互コンダクタンスを大幅に改善したリセス構造のmis型ノーマリオフhemt素子 |
JP2016225578A (ja) * | 2015-06-03 | 2016-12-28 | 富士通株式会社 | 化合物半導体装置及びその製造方法 |
JP2018085414A (ja) * | 2016-11-22 | 2018-05-31 | 富士通株式会社 | 化合物半導体装置 |
WO2019208034A1 (ja) * | 2018-04-27 | 2019-10-31 | ソニーセミコンダクタソリューションズ株式会社 | スイッチングトランジスタ及び半導体モジュール |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2023228611A1 (ja) * | 2022-05-24 | 2023-11-30 | ソニーセミコンダクタソリューションズ株式会社 | 高電子移動度トランジスタ及び半導体装置 |
WO2024048266A1 (ja) * | 2022-09-01 | 2024-03-07 | ソニーグループ株式会社 | 半導体デバイス、半導体モジュールおよび無線通信装置 |
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CN116097409A (zh) | 2023-05-09 |
US20240030332A1 (en) | 2024-01-25 |
JPWO2022049983A1 (ja) | 2022-03-10 |
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