JP5243256B2 - モノリシックに集積化された半導体材料およびデバイス - Google Patents
モノリシックに集積化された半導体材料およびデバイス Download PDFInfo
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- JP5243256B2 JP5243256B2 JP2008538998A JP2008538998A JP5243256B2 JP 5243256 B2 JP5243256 B2 JP 5243256B2 JP 2008538998 A JP2008538998 A JP 2008538998A JP 2008538998 A JP2008538998 A JP 2008538998A JP 5243256 B2 JP5243256 B2 JP 5243256B2
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- silicon
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- semiconductor layer
- crystal semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims description 327
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L31/16—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the semiconductor device sensitive to radiation being controlled by the light source or sources
- H01L31/161—Semiconductor device sensitive to radiation without a potential-jump or surface barrier, e.g. photoresistors
- H01L31/162—Semiconductor device sensitive to radiation without a potential-jump or surface barrier, e.g. photoresistors the light source being a semiconductor device with at least one potential-jump barrier or surface barrier, e.g. a light emitting diode
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Description
本出願は、2005年11月1日に出願された、発明名称が「INTEGRATED LIGHT ARRAYS」である米国仮特許出願第60/732,442号、および2006年4月7日に出願された、発明名称が「INTEGRATED LIGHT ARRAYS」である米国特許出願第60/790204号に基づく米国特許法第119条第(e)項の優先権の利益を主張するものであり、これらの全体は参考として本明細書に援用される。
本発明は、概して半導体構造の製造に関する。より具体的には、本発明は、シリコンおよび他の単結晶半導体材料、および/またはデバイスのモノリシックな集積化に関する。
Claims (20)
- シリコン基板と、
該シリコン基板を覆って配置された第1の単結晶半導体層であって、該第1の単結晶半導体層が緩和シリコンの格子定数とは異なる格子定数を有する、第1の単結晶半導体層と、
第1の領域内の該第1の単結晶半導体層を覆って配置された単結晶シリコン層と、
第2の領域内の該第1の単結晶半導体層の少なくとも一部の上に配置されるか、または、該第2の領域内の該第1の単結晶半導体層の少なくとも一部を覆って配置され、該第1の領域には存在しない、第2の単結晶半導体層であって、該第2の単結晶半導体層が該緩和シリコンの格子定数とは異なる格子定数を有する、第2の単結晶半導体層と
を含む、半導体構造。 - モノリシックに集積化した半導体デバイス構造であって、該構造は、
シリコン基板と、
該シリコン基板を覆って配置された第1の単結晶半導体層であって、該第1の単結晶半導体層が緩和シリコンの格子定数とは異なる格子定数を有する、第1の単結晶半導体層と、
第1の領域内の該第1の単結晶半導体層を覆って配置された単結晶シリコン層と、
該単結晶シリコン層の少なくとも一部を含む素子を含む、少なくとも1つのシリコンベースの電子デバイスと、
第2の領域内の該第1の単結晶半導体層の少なくとも一部の上に配置され、該第1の領域には存在しない、第2の単結晶半導体層であって、該第2の単結晶半導体層が該緩和シリコンの格子定数とは異なる格子定数を有する、第2の単結晶半導体層と、
該第2の単結晶半導体層の少なくとも一部を含むアクティブ領域を含む、少なくとも1つのIII−V族の発光デバイスと
を含む、構造。 - 少なくとも1つのシリコンベースの電子デバイスと、少なくとも1つの前記III−V族の発光デバイスとを結合する電気的相互接続をさらに含む、請求項2に記載の構造。
- 前記単結晶シリコン層の少なくとも一部を含むアクティブ領域を含む、少なくとも1つのシリコンベースの光検出器と、
前記少なくとも1つのIII−V族の発光デバイスと、前記少なくとも1つのシリコンベースの光検出器との間に配置された光導波管であって、該少なくとも1つのIII−V族の発光デバイスによって放射された光の少なくとも一部を、該少なくとも1つのシリコンベースの光検出器に導くように構成された、光導波路とをさらに含む、請求項2に記載の構造。 - モノリシックに集積化した半導体デバイス構造であって、
シリコン基板と、
該シリコン基板を覆って配置された第1の単結晶半導体層であって、該第1の単結晶半導体層が緩和シリコンの格子定数とは異なる格子定数を有する、第1の単結晶半導体層と、
第1の領域内の該第1の単結晶半導体層を覆って配置された単結晶シリコン層と、
該単結晶シリコン層の少なくとも一部を含むアクティブ領域を含む、少なくとも1つのシリコンベースの光検出器と、
第2の領域内の該第1の単結晶半導体層の少なくとも一部の上に配置され、該第1の領域には存在しない、第2の単結晶半導体層であって、該第2の単結晶半導体層が該緩和シリコンの格子定数とは異なる格子定数を有する、第2の単結晶半導体層と、
該第2の単結晶半導体層の少なくとも一部を含むアクティブ領域を含む、少なくとも1つの非シリコン光検出器と
を含む、構造。 - モノリシックに集積化した半導体デバイス構造であって、該構造は、
シリコン基板と、
該シリコン基板を覆って配置された第1の単結晶半導体層であって、該第1の単結晶半導体層が緩和シリコンの格子定数とは異なる格子定数を有する、第1の単結晶半導体層と、
第1の領域内の該第1の単結晶半導体層を覆って配置された単結晶シリコン層と、
該単結晶シリコン層の少なくとも一部を含む素子を含む、少なくとも1つのシリコンベースの電子デバイスと、
第2の領域内の該第1の単結晶半導体層の少なくとも一部の上に配置され、該第1の領域には存在しない、第2の単結晶半導体層であって、該第2の単結晶半導体層が該緩和シリコンの格子定数とは異なる格子定数を有する、第2の単結晶半導体層と、
該第2の単結晶半導体層の少なくとも一部を含む素子を含む、少なくとも1つのIII−V族の電子デバイスと
を含む、構造。 - 前記少なくとも1つのシリコンベースの電子デバイスを、前記少なくともIII−V族の電子デバイスと結合する電気的相互接続をさらに含む、請求項6に記載の構造。
- 前記第1の領域の前記第1の単結晶半導体層を覆って配置された絶縁層をさらに含み、
前記単結晶シリコン層は、該第1の領域の該絶縁層を覆って配置される、請求項1から7に記載の構造。 - 前記第1の単結晶半導体層は、少なくとも2つの単結晶半導体層を含み、該少なくとも2つの単結晶半導体層は、互いを覆って配置され、互いに異なる格子定数であって、前記緩和シリコン、あるいはシリコン−ゲルマニウム層、あるいは該シリコン−ゲルマニウム層の下に配置されたシリコン−ゲルマニウム傾斜層、あるいはIII−V族半導体層とも異なる格子定数を有する、請求項1から8に記載の構造。
- 前記少なくとも2つの単結晶半導体層は、ゲルマニウム層、あるいはGaAs層とInP層、あるいはGaAs層とGaN層を含む、請求項9に記載の構造。
- 前記少なくとも2つの単結晶半導体層は、ゲルマニウム層とGaN層とを含む、請求項9に記載の構造。
- 前記第2の単結晶半導体層の上面は、前記単結晶シリコン層の上面と実質的に同一平面上にある、請求項1から11のいずれかに記載の構造。
- 前記第2の単結晶半導体層は、III−V族の半導体層を含む、請請求項1から12のいずれかに記載の構造。
- 前記III−V族の半導体層を覆って配置されたシリコン層をさらに含み、前記シリコン層は該III−V族の半導体層と接触して配置される、請求項13に記載の構造。
- 前記第2の単結晶半導体層は、前記第1の単結晶層の組成とは異なる組成を有する、請求項1から14のいずれかに記載の構造。
- 前記少なくとも1つのシリコンベースの電子デバイスは、金属酸化膜半導体電界効果トランジスタを含む、請求項1から15のいずれかに記載の構造。
- 前記少なくとも1つのIII−V族電子デバイスは、III−V族の高電子移動度トランジスタ(HEMT)、あるいはIII−V族のヘテロ接合バイポーラトランジスタ(HBT)を含む、請求項6に記載の構造。
- 半導体構造を形成する方法であって、該方法は、
シリコン基板を提供することと、
該シリコン基板を覆って第1の単結晶半導体層を配置することであって、該第1の単結晶半導体層が緩和シリコンの格子定数とは異なる格子定数を有する、ことと、
第1の領域内の該第1の単結晶半導体層を覆って単結晶シリコン層を配置することと、
第2の領域内の該第1の単結晶半導体層の少なくとも一部を覆って第2の単結晶半導体層を配置することであって、該第2の単結晶半導体層が該第1の領域には存在せず、該第2の単結晶半導体層が該緩和シリコンの格子定数とは異なる格子定数を有する、ことと
を含む、方法。 - モノリシックに集積化した半導体デバイス構造を形成する方法であって、該方法は、
シリコン基板を提供することと、
該シリコン基板を覆って第1の単結晶半導体層を配置することであって、該第1の単結晶半導体層が緩和シリコンの格子定数とは異なる格子定数を有する、ことと、
第1の領域内の該第1の単結晶半導体層を覆って絶縁層を配置することと、
該第1の領域内の該絶縁層を覆って単結晶シリコン層を配置することと、
該単結晶シリコン層の少なくとも一部を含むアクティブ領域を含む、少なくとも1つのシリコンベースの光検出器を形成することと、
第2の領域内の該第1の単結晶半導体層の少なくとも一部を覆って、該第1の領域には存在しない、第2の単結晶半導体層を配置することであって、該第2の単結晶半導体層が該緩和シリコンの格子定数とは異なる格子定数を有する、ことと、
該第2の単結晶半導体層の少なくとも一部を含むアクティブ領域を含む、少なくとも1つの非シリコンの光検出器を形成することと
を含む、方法。 - モノリシックに集積化した半導体デバイス構造を形成する方法であって、該方法は、
シリコン基板を提供することと、
該シリコン基板を覆って第1の単結晶半導体層を配置することであって、該第1の単結晶半導体層が緩和シリコンの格子定数とは異なる格子定数を有する、ことと、
第1の領域内の該第1の単結晶半導体層を覆って絶縁層を配置することと、
該第1の領域内の該絶縁層を覆って単結晶シリコン層を配置することと、
該単結晶シリコン層の少なくとも一部を含む素子を含む、少なくとも1つのシリコンベースの電子デバイスを形成することと、
第2の領域内の該第1の単結晶半導体層の少なくとも一部を覆って、該第1の領域には存在しない、第2の単結晶半導体層を配置することであって、該第2の単結晶半導体層が該緩和シリコンの格子定数とは異なる格子定数を有する、ことと、
該第2の単結晶半導体層の少なくとも一部を含む素子を含む、少なくとも1つのIII−V族電子デバイスを形成することと
を含む、方法。
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US8120060B2 (en) | 2012-02-21 |
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US20070105274A1 (en) | 2007-05-10 |
US7705370B2 (en) | 2010-04-27 |
US20090242935A1 (en) | 2009-10-01 |
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