JP5220308B2 - 薄膜トランジスタアレイ基板及びその製造方法 - Google Patents
薄膜トランジスタアレイ基板及びその製造方法 Download PDFInfo
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Description
続いて、ゲート電極11を含む第1基板10の全面にゲート絶縁膜12を蒸着する。
その後、ゲート絶縁膜12の上部に半導体層13及び金属を順に全面蒸着しこれを選択的に除去して、データライン(図示せず)及びソース/ドレイン電極14a/14bを形成する(12S)。ここで、半導体層13は、下部に非晶質シリコン層13aが、上部に不純物層13bが積層されてなる。なお、半導体層13は、ソース/ドレイン電極14a/14bの下部に形成されたもので、ソース/ドレイン電極14a/14bの形成時に共にパターニングされて形成され、ソース/ドレイン電極14a/14b間の領域は、選択的に回折露光をし、ソース/ドレイン電極14a/14b間の対応する金属と半導体層13の不純物層13bを除去する。この時、残された半導体層13の部位は、チャネル領域と定義される。
また、上記目的を達成するための本発明の薄膜トランジスタアレイ基板の製造方法は、基板上に一方向でゲートライン、ゲート電極を形成する段階と、前記ゲートライン、ゲート電極を含む基板上にゲート絶縁膜層、半導体層形成層、データ金属層を順に全面蒸着する段階と、前記データ金属層、半導体層形成層及びゲート絶縁膜層を選択的に除去して前記ゲートラインと交差する方向のデータラインと、半導体層形成部位を残すようにパターニングする段階と、前記データラインを含む前記基板の全面に透明電極を蒸着する段階と、前記半導体層形成部位のチャネルに対応する透明電極、前記データ金属層及び半導体層形成層の所定厚さを除去し、画素領域の所定部分をパターニングし、前記半導体層形成層には半導体層を、前記データ金属層にはソース/ドレイン電極を形成し、前記透明電極には前記ドレイン電極と連結される画素電極を形成する段階と、を備えてなることを特徴とする。
本発明の第1実施形態は、IPSモードにおいて、3つのマスクを通じて製造される薄膜トランジスタアレイ基板及びその製造方法に関する。
本発明の第2実施形態では、TNモードにおいて、3マスクを通じて薄膜トランジスタアレイ基板を形成する。
101 ゲートライン
101a ゲート電極
102 データライン
102a ソース電極
102b ドレイン電極
102c ストレージ附属パターン
103 画素電極
103a 第2ストレージ電極
103b 透明電極パターン
104 半導体層
111 共通ライン
111a 第1ストレージ電極
111b 共通電極
114a ゲート絶縁膜
115a 非晶質シリコン層
116a 不純物層形成層
126 不純物層
121 ゲートパッド配線
122 データパッド配線
123 ゲートパッド端子
125 保護膜
133 データパッド端子
Claims (13)
- 第1マスクを利用して、基板上の一方向にゲートライン、ゲート電極、前記ゲートラインと平行な方向の共通ライン、及び前記共通ラインから分岐する共通電極を形成する第1段階と、
前記ゲートライン及びゲート電極を含む基板上に、ゲート絶縁膜層、半導体層形成層、及びデータ金属層を順に全面蒸着する第2段階と、
第2マスクを利用して、前記データ金属層、半導体層形成層及びゲート絶縁膜層を選択的に除去して、前記ゲートラインと交差する方向のデータライン、半導体層形成部位、及び前記共通電極と交互に配列されるデータパターン層を形成する第3段階と、
前記データラインを含む前記基板の全面に透明電極を蒸着する第4段階と、
第3マスクを利用して、前記半導体層形成部位のチャネル部位に対応する部位の透明電極を選択的に除去するとともに、画素領域の所定部分をパターニングし、前記除去後の前記透明電極をマスクとして、前記データ金属及び半導体層形成層の所定の厚さを除去し、これにより前記チャネル部位の両側に残存する前記データ金属層がソース/ドレイン電極と定義され、前記半導体層形成層は前記チャネル部位を具備し、前記透明電極が前記データパターン層の真上に接続された画素電極を定義する第5段階と、
前記基板の全面に酸化保護膜を全面形成する第6段階と、を備えてなることを特徴とする薄膜トランジスタアレイ基板の製造方法。 - 前記酸化保護膜の形成は、真空チャンバーで酸素プラズマ処理によってなされることを特徴とする請求項1に記載の薄膜トランジスタアレイ基板の製造方法。
- 前記酸化保護膜の形成は、オーブンでなされることを特徴とする請求項1に記載の薄膜トランジスタアレイ基板の製造方法。
- 前記半導体層形成層は、非晶質シリコン層及び不純物層の順に積層されてなることを特徴とする請求項1に記載の薄膜トランジスタアレイ基板の製造方法。
- 前記半導体層形成層を所定厚さ除去する時に、前記チャネルに対応する前記不純物層が除去されることを特徴とする請求項4に記載の薄膜トランジスタアレイ基板の製造方法。
- 前記画素電極は、前記共通電極と交互に配列される形状であることを特徴とする請求項1に記載の薄膜トランジスタアレイ基板の製造方法。
- 前記ゲートラインを形成する時に、前記ゲートラインの端部にゲートパッド配線をさらに形成することを特徴とする請求項1に記載の薄膜トランジスタアレイ基板の製造方法。
- 前記画素電極を形成する時に、前記ゲートパッド配線の上部に、前記画素電極の層と同一層のゲートパッド端子をさらに形成することを特徴とする請求項7に記載の薄膜トランジスタアレイ基板の製造方法。
- 前記データラインを形成する時に、前記データラインの端部にデータパッド配線をさらに形成することを特徴とする請求項1に記載の薄膜トランジスタアレイ基板の製造方法。
- 前記画素電極を形成する時に、前記データパッド配線の上部に前記画素電極の層と同一層のデータパッド端子をさらに形成することを特徴とする請求項9に記載の薄膜トランジスタアレイ基板の製造方法。
- 第1マスクを利用して、基板上の一方向にゲートライン、共通ライン、共通電極、ゲート電極、及びゲートパッド配線を形成する第1段階と、
前記ゲートライン及び前記ゲート電極を含む基板上に、ゲート絶縁膜層、半導体層形成層、及びデータ金属層を順に全面蒸着する第2段階と、
第2マスクを利用して、前記データ金属層、前記半導体層形成層及び前記ゲート絶縁膜層を選択的に除去し、前記ゲートラインと交差する方向のデータライン、半導体層形成部位、前記共通電極と交互に配列されるデータパターン層、及びデータパッド配線を形成する第3段階と、
前記データラインを含む前記基板の全面に透明電極を蒸着する第4段階と、
第3マスクを利用して、前記半導体層形成部位のチャネル部位に対応する部位の透明電極を選択的に除去するとともに、画素領域の所定部分をパターニングし、前記除去後の前記透明電極をマスクとして、前記データ金属及び半導体層形成層の所定の厚さを除去し、これにより前記チャネル部位の両側に残存する前記データ金属層がソース/ドレイン電極と定義され、前記半導体層形成層は前記チャネル部位を具備し、前記透明電極が前記データパターン層の真上に接続された画素電極を定義する第5段階と、
前記基板の全面に酸化保護膜を形成する第6段階と、を備えてなることを特徴とする薄膜トランジスタアレイ基板の製造方法。 - 前記酸化保護膜の形成は、真空チャンバーで酸素プラズマ処理によってなされることを特徴とする請求項11に記載の薄膜トランジスタアレイ基板の製造方法。
- 前記酸化保護膜の形成は、オーブンでなされることを特徴とする請求項11に記載の薄膜トランジスタアレイ基板の製造方法。
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CN1992293B (zh) | 2012-08-29 |
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GB2434687A (en) | 2007-08-01 |
US20070164284A1 (en) | 2007-07-19 |
FR2895805B1 (fr) | 2013-09-27 |
US8058651B2 (en) | 2011-11-15 |
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