JP5158737B2 - フラッシュメモリ素子のフローティングゲート電極形成方法 - Google Patents
フラッシュメモリ素子のフローティングゲート電極形成方法 Download PDFInfo
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- JP5158737B2 JP5158737B2 JP2005176207A JP2005176207A JP5158737B2 JP 5158737 B2 JP5158737 B2 JP 5158737B2 JP 2005176207 A JP2005176207 A JP 2005176207A JP 2005176207 A JP2005176207 A JP 2005176207A JP 5158737 B2 JP5158737 B2 JP 5158737B2
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- floating gate
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- 238000000034 method Methods 0.000 title claims description 51
- 238000005530 etching Methods 0.000 claims description 38
- 230000008569 process Effects 0.000 claims description 37
- 238000002955 isolation Methods 0.000 claims description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
Description
12 素子分離膜
14 トンネル酸化膜
16 ポリシリコン膜
18 有機BARC膜
PR フォトレジストパターン
Claims (4)
- 半導体基板に画定された活性領域と非活性領域との間に所定の厚さの段差が発生するように前記非活性領域に素子分離膜を形成する段階と、
前記素子分離膜が形成された結果物上にトンネル酸化膜、フローティングゲート電極用ポリシリコン膜および有機BARC膜を順次形成した後、前記有機BARC膜の所定の領域にフォトレジストパターンを形成する段階と、
前記フォトレジストパターンをエッチングマスクとしてHBr ガスを用いるエッチング工程で前記有機BARC膜の側壁が傾斜するように前記有機BARC膜をパターニングし、上部面より下部面が広く且つ側壁にスロープを有する、パターニングされた有機BARC膜を形成する段階と、
前記パターニングされた有機BARC膜をエッチングマスクとして下部のフローティングゲート電極用ポリシリコン膜、前記トンネル酸化膜および前記素子分離膜の所定の厚さをパターニングし、側壁にスロープを有するフローティングゲート電極を形成する段階とを含むことを特徴とするフラッシュメモリ素子のフローティングゲート電極形成方法。 - 前記側壁にスロープを有するフローティングゲート電極は、Cl2、O2、HBrおよびN2ガスが混合されたガスを使用するエッチング工程によって形成されることを特徴とする請求項1記載のフラッシュメモリ素子のフローティングゲート電極形成方法。
- 半導体基板に画定された活性領域と非活性領域との間に所定の厚さの段差が発生するように前記非活性領域に素子分離膜を形成する段階と、
前記素子分離膜が形成された結果物上にフローティングゲート電極用ポリシリコン膜を形成し、前記ポリシリコン膜上の前記活性領域に、上部面より下部面が広く且つ側壁にスロープを有する、パターニングされた有機BARC膜を形成する段階と、
前記パターニングされた有機BARC膜をマスクとして前記フローティングゲート電極用ポリシリコン膜および前記素子分離膜の所定の厚さをパターニングし、側壁にスロープを有するフローティングゲート電極を形成する段階とを含むことを特徴とするフラッシュメモリ素子のフローティングゲート電極形成方法。 - 前記上部面より下部面が広く且つ側壁にスロープを有する、パターニングされた有機BARC膜は、前記ポリシリコン膜上に有機BARC膜を形成し、前記有機BARC膜上にフォトレジストパターンを形成した後、前記フォトレジストパターンをエッチングマスクとして、HBrガスが用いられるエッチング工程を行うことにより形成されることを特徴とする請求項3記載のフラッシュメモリ素子のフローティングゲート電極形成方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050019633A KR100647001B1 (ko) | 2005-03-09 | 2005-03-09 | 플래쉬 메모리 소자의 플로팅 게이트 전극 형성방법 |
KR10-2005-0019633 | 2005-03-09 |
Publications (2)
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JP2006253626A JP2006253626A (ja) | 2006-09-21 |
JP5158737B2 true JP5158737B2 (ja) | 2013-03-06 |
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JP2005176207A Expired - Fee Related JP5158737B2 (ja) | 2005-03-09 | 2005-06-16 | フラッシュメモリ素子のフローティングゲート電極形成方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7413960B2 (ja) |
JP (1) | JP5158737B2 (ja) |
KR (1) | KR100647001B1 (ja) |
CN (1) | CN100431104C (ja) |
DE (1) | DE102005030449B4 (ja) |
TW (1) | TWI290373B (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100965047B1 (ko) * | 2007-03-27 | 2010-06-21 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 게이트 패턴 형성 방법 |
JP5266672B2 (ja) | 2007-06-28 | 2013-08-21 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
KR100881136B1 (ko) * | 2007-10-31 | 2009-02-02 | 주식회사 하이닉스반도체 | 향상된 리텐션 특성을 갖는 전하트랩소자의 제조방법 |
KR100976798B1 (ko) | 2008-08-11 | 2010-08-20 | 주식회사 동부하이텍 | 반도체 소자의 제조 방법 |
US8853796B2 (en) * | 2011-05-19 | 2014-10-07 | GLOBALFOUNDIERS Singapore Pte. Ltd. | High-K metal gate device |
CN103515391A (zh) * | 2012-06-29 | 2014-01-15 | 南亚科技股份有限公司 | 非易失性存储器单元及其制造方法 |
US9034564B1 (en) * | 2013-07-26 | 2015-05-19 | Western Digital (Fremont), Llc | Reader fabrication method employing developable bottom anti-reflective coating |
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2005
- 2005-03-09 KR KR1020050019633A patent/KR100647001B1/ko not_active IP Right Cessation
- 2005-06-16 JP JP2005176207A patent/JP5158737B2/ja not_active Expired - Fee Related
- 2005-06-28 DE DE102005030449A patent/DE102005030449B4/de not_active Expired - Fee Related
- 2005-06-29 TW TW094121776A patent/TWI290373B/zh not_active IP Right Cessation
- 2005-06-30 US US11/169,892 patent/US7413960B2/en not_active Expired - Fee Related
- 2005-07-28 CN CNB2005100879768A patent/CN100431104C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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CN100431104C (zh) | 2008-11-05 |
DE102005030449A1 (de) | 2006-09-21 |
DE102005030449B4 (de) | 2011-01-20 |
US20060205158A1 (en) | 2006-09-14 |
TW200633233A (en) | 2006-09-16 |
CN1905133A (zh) | 2007-01-31 |
KR100647001B1 (ko) | 2006-11-23 |
KR20060097082A (ko) | 2006-09-13 |
JP2006253626A (ja) | 2006-09-21 |
US7413960B2 (en) | 2008-08-19 |
TWI290373B (en) | 2007-11-21 |
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