JP5079059B2 - 多層配線基板 - Google Patents

多層配線基板 Download PDF

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Publication number
JP5079059B2
JP5079059B2 JP2010173305A JP2010173305A JP5079059B2 JP 5079059 B2 JP5079059 B2 JP 5079059B2 JP 2010173305 A JP2010173305 A JP 2010173305A JP 2010173305 A JP2010173305 A JP 2010173305A JP 5079059 B2 JP5079059 B2 JP 5079059B2
Authority
JP
Japan
Prior art keywords
main surface
resin insulation
resin
insulation layer
surface side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010173305A
Other languages
English (en)
Japanese (ja)
Other versions
JP2012033790A5 (enExample
JP2012033790A (ja
Inventor
真之介 前田
訓 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP2010173305A priority Critical patent/JP5079059B2/ja
Priority to TW100126899A priority patent/TWI461117B/zh
Priority to KR1020110076655A priority patent/KR101322126B1/ko
Priority to US13/195,290 priority patent/US8530751B2/en
Priority to CN201110225099.1A priority patent/CN102347287B/zh
Publication of JP2012033790A publication Critical patent/JP2012033790A/ja
Publication of JP2012033790A5 publication Critical patent/JP2012033790A5/ja
Application granted granted Critical
Publication of JP5079059B2 publication Critical patent/JP5079059B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H10W78/00—
    • H10W70/685—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H10W70/05—
    • H10W70/60—
    • H10W70/695—
    • H10W72/00—
    • H10W90/401—
    • H10W90/701—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2009—Reinforced areas, e.g. for a specific part of a flexible printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H10W74/15—
    • H10W90/724—
    • H10W90/734—

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2010173305A 2010-08-02 2010-08-02 多層配線基板 Expired - Fee Related JP5079059B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2010173305A JP5079059B2 (ja) 2010-08-02 2010-08-02 多層配線基板
TW100126899A TWI461117B (zh) 2010-08-02 2011-07-29 多層配線基板
KR1020110076655A KR101322126B1 (ko) 2010-08-02 2011-08-01 다층 배선기판
US13/195,290 US8530751B2 (en) 2010-08-02 2011-08-01 Multilayer wiring substrate
CN201110225099.1A CN102347287B (zh) 2010-08-02 2011-08-02 多层布线基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010173305A JP5079059B2 (ja) 2010-08-02 2010-08-02 多層配線基板

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012005848A Division JP5449413B2 (ja) 2012-01-16 2012-01-16 多層配線基板

Publications (3)

Publication Number Publication Date
JP2012033790A JP2012033790A (ja) 2012-02-16
JP2012033790A5 JP2012033790A5 (enExample) 2012-05-10
JP5079059B2 true JP5079059B2 (ja) 2012-11-21

Family

ID=45525552

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010173305A Expired - Fee Related JP5079059B2 (ja) 2010-08-02 2010-08-02 多層配線基板

Country Status (5)

Country Link
US (1) US8530751B2 (enExample)
JP (1) JP5079059B2 (enExample)
KR (1) KR101322126B1 (enExample)
CN (1) CN102347287B (enExample)
TW (1) TWI461117B (enExample)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8780576B2 (en) * 2011-09-14 2014-07-15 Invensas Corporation Low CTE interposer
KR101939236B1 (ko) * 2011-11-10 2019-01-16 삼성전자 주식회사 기판 및 이를 포함하는 전자 장치
US9159649B2 (en) * 2011-12-20 2015-10-13 Intel Corporation Microelectronic package and stacked microelectronic assembly and computing system containing same
US9117730B2 (en) * 2011-12-29 2015-08-25 Ibiden Co., Ltd. Printed wiring board and method for manufacturing printed wiring board
KR101331669B1 (ko) * 2012-03-08 2013-11-20 삼성전기주식회사 전력 모듈용 기판
JP5955102B2 (ja) * 2012-05-29 2016-07-20 京セラ株式会社 配線基板およびその製造方法
US9615447B2 (en) * 2012-07-23 2017-04-04 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Multilayer electronic support structure with integral constructional elements
TW201409633A (zh) * 2012-08-24 2014-03-01 景碩科技股份有限公司 晶片及載板的封裝結構
JP2014063844A (ja) * 2012-09-20 2014-04-10 Sony Corp 半導体装置、半導体装置の製造方法及び電子機器
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
CN104218016A (zh) * 2013-06-04 2014-12-17 宏启胜精密电子(秦皇岛)有限公司 Ic载板及具有该ic载板的半导体器件
KR102149793B1 (ko) * 2013-10-24 2020-08-31 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 휨 제어방법
WO2016103359A1 (ja) 2014-12-24 2016-06-30 ルネサスエレクトロニクス株式会社 半導体装置
CN105789058A (zh) * 2015-01-14 2016-07-20 钰桥半导体股份有限公司 中介层嵌置于加强层中的线路板及其制作方法
US20160204056A1 (en) * 2015-01-14 2016-07-14 Bridge Semiconductor Corporation Wiring board with interposer and dual wiring structures integrated together and method of making the same
CN105870075A (zh) * 2015-01-22 2016-08-17 恒劲科技股份有限公司 基板结构
CN106034374B (zh) * 2015-03-12 2018-10-16 日立汽车系统(苏州）有限公司 防基板变形结构
TWI603505B (zh) * 2015-04-07 2017-10-21 矽品精密工業股份有限公司 封裝基板
JP2016219452A (ja) * 2015-05-14 2016-12-22 富士通株式会社 多層基板及び多層基板の製造方法
US10109588B2 (en) * 2015-05-15 2018-10-23 Samsung Electro-Mechanics Co., Ltd. Electronic component package and package-on-package structure including the same
JP2016219478A (ja) * 2015-05-15 2016-12-22 イビデン株式会社 配線基板及びその製造方法
JP6819599B2 (ja) * 2015-09-25 2021-01-27 大日本印刷株式会社 実装部品、配線基板、電子装置、およびその製造方法
KR102512228B1 (ko) * 2015-10-01 2023-03-21 삼성전기주식회사 절연재 및 이를 포함하는 인쇄회로기판
US9711458B2 (en) * 2015-11-13 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method for chip package
KR101912278B1 (ko) * 2015-12-21 2018-10-29 삼성전기 주식회사 전자 부품 패키지 및 그 제조방법
US9761535B1 (en) * 2016-06-27 2017-09-12 Nanya Technology Corporation Interposer, semiconductor package with the same and method for preparing a semiconductor package with the same
KR102456322B1 (ko) * 2017-11-08 2022-10-19 삼성전기주식회사 기판 스트립 및 이를 포함하는 전자소자 패키지
US10242964B1 (en) 2018-01-16 2019-03-26 Bridge Semiconductor Corp. Wiring substrate for stackable semiconductor assembly and stackable semiconductor assembly using the same
TWI655739B (zh) * 2018-04-19 2019-04-01 南亞電路板股份有限公司 封裝結構及其形成方法
JP7099359B2 (ja) 2019-02-20 2022-07-12 株式会社村田製作所 コイル部品
US11094649B2 (en) * 2020-01-21 2021-08-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11233035B2 (en) * 2020-05-28 2022-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
GB202018676D0 (en) * 2020-11-27 2021-01-13 Graphcore Ltd Controlling warpage of a substrate for mounting a semiconductor die
WO2024209540A1 (ja) * 2023-04-04 2024-10-10 三菱電機株式会社 高周波パッケージおよび高周波パッケージの製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004356569A (ja) 2003-05-30 2004-12-16 Shinko Electric Ind Co Ltd 半導体装置用パッケージ
JP4342366B2 (ja) * 2004-04-09 2009-10-14 日本特殊陶業株式会社 配線基板の製造方法
JP2006287056A (ja) * 2005-04-01 2006-10-19 Ngk Spark Plug Co Ltd 配線基板および配線基板の製造方法
JP2008078683A (ja) 2005-08-29 2008-04-03 Shinko Electric Ind Co Ltd 多層配線基板
JP4072176B2 (ja) 2005-08-29 2008-04-09 新光電気工業株式会社 多層配線基板の製造方法
JP2008118155A (ja) 2007-12-20 2008-05-22 Shinko Electric Ind Co Ltd 半導体装置用パッケージ
JP2008118154A (ja) 2007-12-20 2008-05-22 Shinko Electric Ind Co Ltd 半導体装置用パッケージ
JP5179920B2 (ja) * 2008-03-28 2013-04-10 日本特殊陶業株式会社 多層配線基板
JP5290017B2 (ja) * 2008-03-28 2013-09-18 日本特殊陶業株式会社 多層配線基板及びその製造方法
TWI475932B (zh) * 2008-09-29 2015-03-01 日本特殊陶業股份有限公司 帶有補強材之配線基板
JP5306789B2 (ja) * 2008-12-03 2013-10-02 日本特殊陶業株式会社 多層配線基板及びその製造方法
JP4473935B1 (ja) * 2009-07-06 2010-06-02 新光電気工業株式会社 多層配線基板

Also Published As

Publication number Publication date
KR20120022593A (ko) 2012-03-12
TW201220980A (en) 2012-05-16
US20120024582A1 (en) 2012-02-02
CN102347287A (zh) 2012-02-08
TWI461117B (zh) 2014-11-11
US8530751B2 (en) 2013-09-10
CN102347287B (zh) 2015-01-28
JP2012033790A (ja) 2012-02-16
KR101322126B1 (ko) 2013-10-28

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