JP5036719B2 - 耐放射線性のあるアイソレーション構造及びその製造方法 - Google Patents

耐放射線性のあるアイソレーション構造及びその製造方法 Download PDF

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JP5036719B2
JP5036719B2 JP2008535745A JP2008535745A JP5036719B2 JP 5036719 B2 JP5036719 B2 JP 5036719B2 JP 2008535745 A JP2008535745 A JP 2008535745A JP 2008535745 A JP2008535745 A JP 2008535745A JP 5036719 B2 JP5036719 B2 JP 5036719B2
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channel
substrate
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wafer
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JP2009516361A (ja
JP2009516361A5 (enExample
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モーリス、ウェズリー・エイチ
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Silicon Space Tech Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/378—Contact regions to the substrate regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
JP2008535745A 2005-10-14 2006-10-16 耐放射線性のあるアイソレーション構造及びその製造方法 Active JP5036719B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US72703105P 2005-10-14 2005-10-14
US60/727,031 2005-10-14
US11/581,561 US8278719B2 (en) 2005-10-14 2006-10-16 Radiation hardened isolation structures and fabrication methods
US11/581,561 2006-10-16
PCT/US2006/040224 WO2007061531A2 (en) 2005-10-14 2006-10-16 Radiation hardened isolation structures and fabrication methods

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JP2009516361A JP2009516361A (ja) 2009-04-16
JP2009516361A5 JP2009516361A5 (enExample) 2009-12-03
JP5036719B2 true JP5036719B2 (ja) 2012-09-26

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US (3) US8278719B2 (enExample)
EP (1) EP1949425A4 (enExample)
JP (1) JP5036719B2 (enExample)
WO (1) WO2007061531A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101588865B1 (ko) * 2013-09-30 2016-01-25 (주)아트로닉스 반도체 소자 및 그 제조 방법

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7141468B2 (en) * 2003-10-27 2006-11-28 Texas Instruments Incorporated Application of different isolation schemes for logic and embedded memory
US8253196B2 (en) 2004-01-29 2012-08-28 Enpirion, Inc. Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same
US7230302B2 (en) 2004-01-29 2007-06-12 Enpirion, Inc. Laterally diffused metal oxide semiconductor device and method of forming the same
US8212316B2 (en) * 2004-01-29 2012-07-03 Enpirion, Inc. Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same
US8253197B2 (en) 2004-01-29 2012-08-28 Enpirion, Inc. Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same
US8212317B2 (en) * 2004-01-29 2012-07-03 Enpirion, Inc. Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same
US8253195B2 (en) * 2004-01-29 2012-08-28 Enpirion, Inc. Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same
US8212315B2 (en) * 2004-01-29 2012-07-03 Enpirion, Inc. Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same
US7304354B2 (en) 2004-02-17 2007-12-04 Silicon Space Technology Corp. Buried guard ring and radiation hardened isolation structures and fabrication methods
JP5036719B2 (ja) * 2005-10-14 2012-09-26 シリコン・スペース・テクノロジー・コーポレイション 耐放射線性のあるアイソレーション構造及びその製造方法
US20080142899A1 (en) * 2006-08-04 2008-06-19 Silicon Space Technology Corporation Radiation immunity of integrated circuits using backside die contact and electrically conductive layers
US8497167B1 (en) * 2007-01-17 2013-07-30 National Semiconductor Corporation EDS protection diode with pwell-nwell resurf
US8495550B2 (en) * 2009-01-15 2013-07-23 Klas Olof Lilja Soft error hard electronic circuit and layout
US9083341B2 (en) 2008-01-17 2015-07-14 Robust Chip Inc. Soft error resilient circuit design method and logic cells
JP2011512026A (ja) * 2008-01-17 2011-04-14 リルジャ，クラス，オロフ ソフト−エラー・ハード・エレクトロニクス及び耐放射線論理セルのためのレイアウト方法
US8468484B2 (en) 2008-01-17 2013-06-18 Klas Olof Lilja Layout method for soft-error hard electronics, and radiation hardened logic cell
US20140157223A1 (en) * 2008-01-17 2014-06-05 Klas Olof Lilja Circuit and layout design methods and logic cells for soft error hard integrated circuits
JP4748224B2 (ja) * 2009-01-23 2011-08-17 ソニー株式会社 半導体集積回路
US8247280B2 (en) * 2009-10-20 2012-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Integration of low and high voltage CMOS devices
JP2011146513A (ja) * 2010-01-14 2011-07-28 Renesas Electronics Corp 半導体装置
US8367511B2 (en) 2011-03-07 2013-02-05 Macronix International Co., Ltd. Manufacturing method for high voltage transistor
US8614111B2 (en) * 2011-07-25 2013-12-24 International Business Machines Corporation Fully depleted silicon on insulator neutron detector
US9396947B2 (en) 2011-08-25 2016-07-19 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9378956B2 (en) 2011-08-25 2016-06-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9378955B2 (en) 2011-08-25 2016-06-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US9312133B2 (en) 2011-08-25 2016-04-12 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
WO2013028983A1 (en) * 2011-08-25 2013-02-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US20130049175A1 (en) * 2011-08-25 2013-02-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US20130049178A1 (en) * 2011-08-25 2013-02-28 Aeroflex Colorado Springs Inc. Wafer structure for electronic integrated circuit manufacturing
US8853825B2 (en) 2011-09-27 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. ESD protection apparatus
US8972819B2 (en) 2011-11-22 2015-03-03 Silicon Space Technology Corporation Memory circuit incorporating radiation-hardened memory scrub engine
US8614121B2 (en) 2011-11-29 2013-12-24 International Business Machines Corporation Method of manufacturing back gate triggered silicon controlled rectifiers
KR101383510B1 (ko) * 2011-12-07 2014-04-08 경희대학교 산학협력단 Ｓｏｉ 로직 회로의 바이어스 회로
US8723269B2 (en) 2011-12-27 2014-05-13 Leonard Richard Rockett Buried power grid designs for improved radiation hardness in CMOS technologies
US8692291B2 (en) * 2012-03-27 2014-04-08 International Business Machines Corporation Passive devices for FinFET integrated circuit technologies
US9219056B2 (en) * 2012-03-27 2015-12-22 International Business Machines Corporation Passive devices for FinFET integrated circuit technologies
CN103855134A (zh) 2012-11-30 2014-06-11 英力股份有限公司 包括耦合至解耦合器件的半导体器件的装置
US9773884B2 (en) * 2013-03-15 2017-09-26 Hrl Laboratories, Llc III-nitride transistor with engineered substrate
JP6115243B2 (ja) * 2013-03-28 2017-04-19 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
US9702925B2 (en) 2014-10-15 2017-07-11 Nxp Usa, Inc. Semiconductor device with upset event detection and method of making
WO2016132418A1 (ja) * 2015-02-18 2016-08-25 富士電機株式会社 半導体集積回路
US9659979B2 (en) * 2015-10-15 2017-05-23 International Business Machines Corporation Sensors including complementary lateral bipolar junction transistors
RU2638584C2 (ru) * 2015-11-17 2017-12-14 Акционерное общество "Воронежский завод полупроводниковых приборов-сборка" Периферия полупроводниковых приборов с повышенной устойчивостью к ионизирующему излучению
US10038058B2 (en) 2016-05-07 2018-07-31 Silicon Space Technology Corporation FinFET device structure and method for forming same
JP6733425B2 (ja) * 2016-08-29 2020-07-29 富士電機株式会社 半導体集積回路及び半導体モジュール
US9679888B1 (en) * 2016-08-30 2017-06-13 Globalfoundries Inc. ESD device for a semiconductor structure
US10319716B2 (en) * 2017-05-05 2019-06-11 Newport Fab, Llc Substrate isolation for low-loss radio frequency (RF) circuits
US10290631B2 (en) * 2017-05-05 2019-05-14 Newport Fab, Llc Linearity and lateral isolation in a BiCMOS process through counter-doping of epitaxial silicon region
US10410934B2 (en) * 2017-12-07 2019-09-10 Micron Technology, Inc. Apparatuses having an interconnect extending from an upper conductive structure, through a hole in another conductive structure, and to an underlying structure
US10825715B2 (en) 2018-11-08 2020-11-03 Silicon Space Technologies Corporation Structures for improving radiation hardness and eliminating latch-up in integrated circuits
KR102009458B1 (ko) * 2019-04-15 2019-08-09 경희대학교 산학협력단 완전 공핍형 실리콘 온 인슐레이터 공정을 이용한 메모리 장치의 안정도에 대한 총 이온화 선량 효과의 측정 방법
US11461531B2 (en) * 2019-04-29 2022-10-04 Silicon Space Technology Corporation Learning-based analyzer for mitigating latch-up in integrated circuits
CN110190121B (zh) * 2019-05-29 2023-04-25 电子科技大学 具有瞬时剂量率辐射加固结构的横向soi高压器件
CN115346877B (zh) * 2022-08-24 2025-08-01 中国电子科技集团公司第五十八研究所 一种提高n型Flash存储器件抗辐射性能的方法

Family Cites Families (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4054894A (en) * 1975-05-27 1977-10-18 Rca Corporation Edgeless transistor
US4203126A (en) * 1975-11-13 1980-05-13 Siliconix, Inc. CMOS structure and method utilizing retarded electric field for minimum latch-up
JPS5389681A (en) * 1977-01-19 1978-08-07 Hitachi Ltd Mis type semiconductor device
FR2498812A1 (fr) 1981-01-27 1982-07-30 Thomson Csf Structure de transistors dans un circuit integre et son procede de fabrication
JPS59181658A (ja) * 1983-03-31 1984-10-16 Toshiba Corp 半導体装置
US4639761A (en) * 1983-12-16 1987-01-27 North American Philips Corporation Combined bipolar-field effect transistor resurf devices
JPH0770604B2 (ja) 1985-04-17 1995-07-31 ソニー株式会社 相補型電界効果トランジスタの製法
JPS62250671A (ja) 1986-04-24 1987-10-31 Agency Of Ind Science & Technol 半導体装置
US4980747A (en) * 1986-12-22 1990-12-25 Texas Instruments Inc. Deep trench isolation with surface contact to substrate
JPH01189955A (ja) * 1988-01-26 1989-07-31 Nec Corp 半導体装置
JPH01265555A (ja) 1988-04-15 1989-10-23 Ricoh Co Ltd ラッチアップ防止手段をもつ半導体装置
JPH01273346A (ja) 1988-04-25 1989-11-01 Nec Kansai Ltd 半導体装置
JP2660056B2 (ja) * 1989-09-12 1997-10-08 三菱電機株式会社 相補型ｍｏｓ半導体装置
US5138420A (en) * 1989-11-24 1992-08-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having first and second type field effect transistors separated by a barrier
JP2991386B2 (ja) 1990-01-11 1999-12-20 三菱電機株式会社 半導体装置の製造方法
JPH04139758A (ja) 1990-10-01 1992-05-13 Toshiba Corp 半導体装置およびその製造方法
JPH0567753A (ja) * 1991-04-17 1993-03-19 Mitsubishi Electric Corp 二重構造ウエルを有する半導体装置およびその製造方法
US5386136A (en) * 1991-05-06 1995-01-31 Siliconix Incorporated Lightly-doped drain MOSFET with improved breakdown characteristics
USH1435H (en) * 1991-10-21 1995-05-02 Cherne Richard D SOI CMOS device having body extension for providing sidewall channel stop and bodytie
US5376816A (en) * 1992-06-24 1994-12-27 Nec Corporation Bi-cmos integrated circuit device having buried region use in common for bipolar and mos transistors
US5220192A (en) * 1992-07-10 1993-06-15 Lsi Logic Radiation hardened CMOS structure using an implanted P guard structure and method for the manufacture thereof
JPH10509276A (ja) 1993-04-28 1998-09-08 エス・イー・エイチ・アメリカ，アイ・エヌ・シー Ｃｍｏｓ集積回路用のエピタキシャル半導体ウエーハ
JPH06350083A (ja) * 1993-06-11 1994-12-22 Natl Space Dev Agency Japan<Nasda> セラミックス封止型半導体装置
JPH07169922A (ja) * 1993-09-29 1995-07-04 At & T Global Inf Solutions Internatl Inc シリコン制御整流器
JP2800702B2 (ja) * 1994-10-31 1998-09-21 日本電気株式会社 半導体装置
US5501993A (en) * 1994-11-22 1996-03-26 Genus, Inc. Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation
US5719733A (en) * 1995-11-13 1998-02-17 Lsi Logic Corporation ESD protection for deep submicron CMOS devices with minimum tradeoff for latchup behavior
US5904551A (en) * 1996-04-12 1999-05-18 Lsi Logic Corporation Process for low energy implantation of semiconductor substrate using channeling to form retrograde wells
US5966599A (en) * 1996-05-21 1999-10-12 Lsi Logic Corporation Method for fabricating a low trigger voltage silicon controlled rectifier and thick field device
JP3077592B2 (ja) * 1996-06-27 2000-08-14 日本電気株式会社 デジタル回路とアナログ回路が混在する半導体集積回路装置およびその製造方法
CN1196832A (zh) * 1996-06-28 1998-10-21 精工爱普生株式会社 薄膜晶体管及其制造方法和使用该薄膜晶体管的电路和液晶显示装置
KR100233558B1 (ko) 1996-06-29 1999-12-01 김영환 반도체 소자의 제조방법
KR0184158B1 (ko) * 1996-07-13 1999-04-15 문정환 반도체장치의 자기 정합정 금속 배선 형성 방법
US5728612A (en) * 1996-07-19 1998-03-17 Lsi Logic Corporation Method for forming minimum area structures for sub-micron CMOS ESD protection in integrated circuit structures without extra implant and mask steps, and articles formed thereby
US5835986A (en) * 1996-09-06 1998-11-10 Lsi Logic Corporation Electrostatic discharge (ESD) structure and buffer driver structure for providing ESD and latchup protection for integrated circuit structures in minimized I/O space
US5880515A (en) * 1996-09-30 1999-03-09 Lsi Logic Corporation Circuit isolation utilizing MeV implantation
US5821572A (en) * 1996-12-17 1998-10-13 Symbios, Inc. Simple BICMOS process for creation of low trigger voltage SCR and zener diode pad protection
US5963801A (en) * 1996-12-19 1999-10-05 Lsi Logic Corporation Method of forming retrograde well structures and punch-through barriers using low energy implants
US5858828A (en) * 1997-02-18 1999-01-12 Symbios, Inc. Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor
JP3528554B2 (ja) * 1997-12-04 2004-05-17 セイコーエプソン株式会社 半導体装置
US6165821A (en) * 1998-02-09 2000-12-26 International Rectifier Corp. P channel radhard device with boron diffused P-type polysilicon gate
US6137142A (en) * 1998-02-24 2000-10-24 Sun Microsystems, Inc. MOS device structure and method for reducing PN junction leakage
US6136672A (en) * 1998-04-17 2000-10-24 Lucent Technologies Inc. Process for device fabrication using a high-energy boron implant
DE19821726C1 (de) * 1998-05-14 1999-09-09 Texas Instruments Deutschland Ingegrierte CMOS-Schaltung für die Verwendung bei hohen Frequenzen
US5985705A (en) * 1998-06-30 1999-11-16 Lsi Logic Corporation Low threshold voltage MOS transistor and method of manufacture
JP2000049237A (ja) 1998-07-28 2000-02-18 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6211555B1 (en) * 1998-09-29 2001-04-03 Lsi Logic Corporation Semiconductor device with a pair of transistors having dual work function gate electrodes
US6069048A (en) * 1998-09-30 2000-05-30 Lsi Logic Corporation Reduction of silicon defect induced failures as a result of implants in CMOS and other integrated circuits
US6225207B1 (en) * 1998-10-01 2001-05-01 Applied Materials, Inc. Techniques for triple and quadruple damascene fabrication
US6395611B1 (en) * 1998-11-04 2002-05-28 Agere Systems Guardian Corp. Inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit
US6144076A (en) * 1998-12-08 2000-11-07 Lsi Logic Corporation Well formation For CMOS devices integrated circuit structures
US6232165B1 (en) * 1998-12-09 2001-05-15 Winbond Electronics Corporation Buried guard rings and method for forming the same
KR100275962B1 (ko) * 1998-12-30 2001-02-01 김영환 반도체장치 및 그의 제조방법_
KR100284746B1 (ko) * 1999-01-15 2001-03-15 김덕중 소스 영역 하부의 바디 저항이 감소된 전력용 디모스 트랜지스터
US6063672A (en) * 1999-02-05 2000-05-16 Lsi Logic Corporation NMOS electrostatic discharge protection device and method for CMOS integrated circuit
US7575969B2 (en) * 2000-03-02 2009-08-18 Texas Instruments Incorporated Buried layer and method
US6762128B2 (en) 2000-06-09 2004-07-13 Bae Systems Apparatus and method for manufacturing a semiconductor circuit
US6472715B1 (en) * 2000-09-28 2002-10-29 Lsi Logic Corporation Reduced soft error rate (SER) construction for integrated circuit structures
JP3950294B2 (ja) 2000-11-16 2007-07-25 シャープ株式会社 半導体装置
US6492270B1 (en) * 2001-03-19 2002-12-10 Taiwan Semiconductor Manufacturing Company Method for forming copper dual damascene
US20020173077A1 (en) * 2001-05-03 2002-11-21 Ho Tzong Da Thermally enhanced wafer-level chip scale package and method of fabricating the same
US6706583B1 (en) * 2001-10-19 2004-03-16 Lsi Logic Corporation High speed low noise transistor
US6818528B2 (en) * 2001-10-24 2004-11-16 International Business Machines Corporation Method for multi-depth trench isolation
US6885078B2 (en) * 2001-11-09 2005-04-26 Lsi Logic Corporation Circuit isolation utilizing MeV implantation
US6664608B1 (en) * 2001-11-30 2003-12-16 Sun Microsystems, Inc. Back-biased MOS device
US6673635B1 (en) * 2002-06-28 2004-01-06 Advanced Micro Devices, Inc. Method for alignment mark formation for a shallow trench isolation process
US6787858B2 (en) * 2002-10-16 2004-09-07 Freescale Semiconductor, Inc. Carrier injection protection structure
US6847065B1 (en) * 2003-04-16 2005-01-25 Raytheon Company Radiation-hardened transistor fabricated by modified CMOS process
US6864152B1 (en) * 2003-05-20 2005-03-08 Lsi Logic Corporation Fabrication of trenches with multiple depths on the same substrate
US7304354B2 (en) 2004-02-17 2007-12-04 Silicon Space Technology Corp. Buried guard ring and radiation hardened isolation structures and fabrication methods
JP2005353703A (ja) * 2004-06-08 2005-12-22 Nec Compound Semiconductor Devices Ltd 電界効果型トランジスタ
JP5036719B2 (ja) 2005-10-14 2012-09-26 シリコン・スペース・テクノロジー・コーポレイション 耐放射線性のあるアイソレーション構造及びその製造方法
US20080142899A1 (en) 2006-08-04 2008-06-19 Silicon Space Technology Corporation Radiation immunity of integrated circuits using backside die contact and electrically conductive layers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101588865B1 (ko) * 2013-09-30 2016-01-25 (주)아트로닉스 반도체 소자 및 그 제조 방법

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WO2007061531A2 (en) 2007-05-31
JP2009516361A (ja) 2009-04-16
US20130059421A1 (en) 2013-03-07
US20070141794A1 (en) 2007-06-21
US8278719B2 (en) 2012-10-02
US8252642B2 (en) 2012-08-28

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