JP6733425B2 - 半導体集積回路及び半導体モジュール - Google Patents
半導体集積回路及び半導体モジュール Download PDFInfo
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Description
本発明の実施の形態に係る半導体集積回路40aは、比較的低容量のインバータ等において用いられるHVICであり、例えば600V〜1200V程度の電圧に耐えて動作する電力変換用ブリッジ回路の制御用ICである。半導体集積回路40aは、図1に示すように、低濃度の第1導電型(p−型)の半導体基板1と、図1中の左上側に示すように、この半導体基板1の上部に設けられた第2導電型(n型)の第1ウェル領域2と、を備える。
一方、比較例に係る半導体集積回路40zの場合、図8に示すように、半導体基板1と裏面電極層11の間に絶縁層10が設けられていない。そのため、負電圧サージの絶対値が大きいと、第1寄生ダイオードPD1及び第2寄生ダイオードPD2がオンし、第4経路R4、第5経路R5及び第6経路R6を介して、GND端子46側やVB端子44側へ流れる電流が大きくなる。
本発明は上記の開示した実施の形態によって説明したが、この開示の一部をなす論述及び図面は、本発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかになると考えられるべきである。
2 第1ウェル領域
3 第2ウェル領域
4 耐圧領域
5 第1分離領域
6a 第2分離領域
8 第1コンタクト領域
8a 第1コンタクト電極
10 絶縁層
11 裏面電極層
14 第2コンタクト領域
14a 第2コンタクト電極
15 第1分離コンタクト領域
15a 第1分離コンタクト電極
16 第2分離コンタクト領域
16a 第2分離コンタクト電極
20 層間絶縁膜
22 第3ウェル領域
23 第4ウェル領域
24 第4コンタクト領域
24a 第4コンタクト電極
28 第3コンタクト領域
28a 第3コンタクト電極
30 絶縁回路基板
31a〜31c 導体層
32a〜32c 接合層
40a〜40d,40z 半導体集積回路
41 入力端子
42 出力端子
43 VS端子
44 VB端子
45 VCC端子
46 GND端子
51 接続点
57 負荷
61 ソース領域
62 ドレイン領域
63 ソース電極
64 ドレイン電極
65 ゲート電極
71 ソース領域
72 ドレイン領域
73 ソース電極
74 ドレイン電極
75 ゲート電極
80 空乏層
FWD1〜FWD6 還流ダイオード
PD1 第1寄生ダイオード
PD2 第2寄生ダイオード
R1〜R6 第1経路〜第6経路
S1〜S6 スイッチング素子
d 距離
Claims (10)
- 第1導電型の半導体基板と、
前記半導体基板の上部に設けられた第2導電型の第1ウェル領域と、
前記第1ウェル領域の上部に設けられた第1導電型の第2ウェル領域と、
前記第1ウェル領域の直下の前記半導体基板の下部に前記第1ウェル領域から離間して設けられた絶縁層と、
前記絶縁層の下に設けられた裏面電極層と、を有し、
さらに、前記第1ウェル領域の上部に設けられた第1導電型の第1主電極領域及び第2主電極領域を有する第1能動素子と、前記第2ウェル領域の上部に設けられた第2導電型の第3主電極領域及び第4主電極領域を有する第2能動素子と、を備え、
前記第1能動素子及び前記第2能動素子によって、電力変換用ブリッジ回路のハイサイド駆動回路が構成されていることを特徴とする半導体集積回路。 - 前記半導体基板の上部に前記第1ウェル領域から離間して設けられ、かつ基準電位が印加される第1導電型の分離領域を更に備えることを特徴とする請求項1に記載の半導体集積回路。
- 第1導電型の半導体基板と、
前記半導体基板の上部に設けられた第2導電型の第1ウェル領域と、
前記第1ウェル領域の上部に設けられた第1導電型の第2ウェル領域と、
前記第1ウェル領域の直下の前記半導体基板の下部に前記第1ウェル領域から離間して設けられた絶縁層と、
前記絶縁層の下に設けられた裏面電極層と、を備え、
さらに、前記半導体基板の上部に前記第1ウェル領域から離間して設けられ、かつ基準電位が印加される第1導電型の分離領域を備えることを特徴とする半導体集積回路。 - 前記半導体基板の上部の前記第1ウェル領域と前記分離領域の間に設けられた第2導電型の耐圧領域を更に備えることを特徴とする請求項2又は請求項3に記載の半導体集積回路。
- 前記第1ウェル領域には第1電位が印加され、
前記第2ウェル領域には第1電位とは異なる第2電位が印加されることを特徴とする請求項1から請求項4のいずれか一項に記載の半導体集積回路。 - 前記第1ウェル領域と前記絶縁層との間の距離は、前記第1ウェル領域に前記第1電位を印加し、前記第2ウェル領域に第2電位を印加したときに、前記半導体基板と前記第1ウェル領域とのpn接合界面部から広がる空乏層が、前記絶縁層から離間する長さであることを特徴とする請求項5に記載の半導体集積回路。
- 第1導電型の半導体基板と、
前記半導体基板の上部に設けられた第2導電型の第1ウェル領域と、
前記第1ウェル領域の上部に設けられた第1導電型の第2ウェル領域と、
前記第1ウェル領域の直下の前記半導体基板の下部に前記第1ウェル領域から離間して設けられた絶縁層と、
前記絶縁層の下に設けられた裏面電極層と、を有する半導体集積回路と、
前記半導体集積回路を、表面に設けられた導電層の上に搭載する絶縁回路基板と、
前記導電層及び前記裏面電極層の間に介在し前記裏面電極層及び前記導電層を接合する接合層と、
を備えることを特徴とする半導体モジュール。 - 前記第1ウェル領域の上部に設けられた第1導電型の第1主電極領域及び第2主電極領域を有する第1能動素子と、
前記第2ウェル領域の上部に設けられた第2導電型の第3主電極領域及び第4主電極領域を有する第2能動素子と、
を更に備えることを特徴とする請求項7に記載の半導体モジュール。 - 前記絶縁回路基板の上に搭載され、前記第1能動素子及び前記第2能動素子によって駆動制御されるスイッチング素子を更に備えることを特徴とする請求項8に記載の半導体モジュール。
- 前記半導体集積回路及び前記スイッチング素子は、同じ高さで搭載されていることを特徴とする請求項9に記載の半導体モジュール。
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