JP4944605B2 - 基板中の電気的接続 - Google Patents
基板中の電気的接続 Download PDFInfo
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- 238000000034 method Methods 0.000 claims description 65
- 239000000758 substrate Substances 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 24
- 239000011810 insulating material Substances 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000004377 microelectronic Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 2
- 238000009760 electrical discharge machining Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 79
- 238000011049 filling Methods 0.000 description 6
- 239000007858 starting material Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 235000016496 Panda oleosa Nutrition 0.000 description 1
- 240000000220 Panda oleosa Species 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000007514 turning Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0006—Interconnects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Micromachines (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Combinations Of Printed Boards (AREA)
- Manufacturing Of Electrical Connectors (AREA)
Description
図7に従来技術である電気的接続の構造を示す(US−6,002,177の図3に対応する)。チップの2つの両面の間に電気的接続を与えるために、シリコンチップ内にホールの穴を開け、前記ホールの内壁を金属化する
標準的なトレンチエッチングがシリコンウエハに施される。ウエハは直径100mm、厚さ500μmである。
したがって、この問題を改善するために、追加で、図2と関連して説明される浅いエッチングが行われる。
図10に完成したビアの長方形の形状を有するアレイの例を示す。
図11は、エッチングがウエハの両面から行われる実施態様によって作られたビアのアレイを示す。
図12にMEMS素子、特に偏光可能なマイクロミラーアレイを作るための概略のプロセス手順を示す。
図13に、MEMS素子を作るためのプロセス手順のさらなる態様を概略的に図示する。
本発明は、図面を参照し以下に説明される。
Claims (20)
- マイクロエレクトロニック及び/又はマイクロメカニック素子を製造するための出発基板を製造する方法であって、
第1表面及び第2表面を有する半導電性又は導電性の材料からなるウエハを用意し、
第1表面にトレンチを作成し、前記トレンチが、ウエハを貫通して伸びておらず、前記ウエハの一部分を囲む、閉じた環の形状のパターンで規定され、
前記トレンチ内に絶縁性材料を付与し、
前記第2表面を選択的に薄化して、前記トレンチ内の絶縁性材料を露出させ、及び、少なくとも一つのキャビティであって、該キャビティの底部が、前記トレンチの露出された表面及びその周囲の所定距離に広がる、キャビティを形成して、前記トレンチによって規定される前記ウエハの一部分を、前記ウエハからなる周辺材料から完全に分離し、分離された一部分の上側表面及び下側表面を露出させた状態で絶縁性囲いを設け、且つ、該キャビティ内であって且つ該キャビティの底部表面上のみに電気的接続を形成する、方法。 - ウエハが、前記キャビティの底部に対応する深さに設けられたエッチングストップ層を含み、それによってトレンチが前記エッチングストップ層によって定められた所定の深さにエッチングされ、かつ、ウエハの薄化が前記エッチングストップ層の除去を含む請求項1記載の方法。
- トレンチがエッチングプロセスによって作成される請求項1又は2記載の方法。
- トレンチがレーザー系加工プロセスによって作成される請求項1又は2記載の方法。
- トレンチが放電加工プロセスによって作成される請求項1又は2記載の方法。
- 絶縁性材料の付与が、前記絶縁性材料を前記トレンチ内に導入することにより行なわれる請求項1〜5のいずれか1項記載の方法。
- 前記トレンチが少なくとも部分的に前記絶縁性材料で満たされる請求項6記載の方法。
- トレンチによって囲まれた材料を選択的にドーピングするために、ドーピング材料をトレンチ内に導入することをさらに含む、請求項1〜7のいずれか1項記載の方法。
- より深いドーピングを可能とするために、ウエハ内の前記トレンチによって囲まれた領域内に、少なくとも一つのさらなるトレンチ又はホールを設けることをさらに含む、請求項8記載の方法。
- マイクロエレクトロニック及び/又はマイクロメカニック素子を製造するための出発基板であって、
第1表面及び第2表面を有する半導電性又は導電性の材料からなるウエハ;
前記ウエハを貫通して伸びる少なくとも一つの電気的接続部を含み、
電気的接続部が絶縁性材料のトレンチによってウエハからなる周辺材料から絶縁され、
前記電気的接続部が前記ウエハから作られており、
ウエハが、前記第2表面に一つ以上の部分的なキャビティであって、該キャビティの底部において前記トレンチの絶縁性材料が露出されており且つ該キャビティの底部が、該露出された前記トレンチの表面及びその周囲の所定距離に広がる、キャビティを有し、絶縁された電気的接続部が前記キャビティ内であって且つ該キャビティの底部表面上にあることを特徴とする基板。 - 前記ウエハが半導体ウエハである請求項10記載の基板。
- 前記ウエハがシリコンウエハである請求項11記載の基板。
- 前記ウエハの厚さが200〜5000μmである、請求項10〜12のいずれか1項記載の基板。
- 前記ウエハの厚さが300〜3000μmである、請求項13記載の基板。
- 前記ウエハの厚さが400〜1000μmである、請求項14記載の基板。
- 絶縁性材料の層の厚さが1〜20μmである、請求項10〜15のいずれか1項記載の基板。
- 絶縁性材料の層の厚さが8〜12μmである、請求項16記載の基板。
- 電気的接続部間のピッチが10μmより大きい、請求項10〜17のいずれか1項記載の基板。
- 電気的接続部間のピッチが50〜100μmである請求項18記載の基板。
- ウエハが平坦である請求項10〜19のいずれか1項記載の基板。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE0300784-6 | 2003-03-21 | ||
SE0300784A SE526366C3 (sv) | 2003-03-21 | 2003-03-21 | Elektriska anslutningar i substrat |
PCT/SE2004/000439 WO2004084300A1 (en) | 2003-03-21 | 2004-03-22 | Electrical connections in substrates |
Publications (2)
Publication Number | Publication Date |
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JP2006521022A JP2006521022A (ja) | 2006-09-14 |
JP4944605B2 true JP4944605B2 (ja) | 2012-06-06 |
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Application Number | Title | Priority Date | Filing Date |
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JP2006507977A Expired - Lifetime JP4944605B2 (ja) | 2003-03-21 | 2004-03-22 | 基板中の電気的接続 |
Country Status (10)
Country | Link |
---|---|
US (1) | US7560802B2 (ja) |
EP (1) | EP1609180B1 (ja) |
JP (1) | JP4944605B2 (ja) |
KR (1) | KR101123002B1 (ja) |
CN (1) | CN1791975B (ja) |
CA (1) | CA2519893C (ja) |
DK (1) | DK1609180T3 (ja) |
HK (1) | HK1084236A1 (ja) |
SE (1) | SE526366C3 (ja) |
WO (1) | WO2004084300A1 (ja) |
Families Citing this family (71)
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US8154131B2 (en) * | 2005-06-14 | 2012-04-10 | Cufer Asset Ltd. L.L.C. | Profiled contact |
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US7838997B2 (en) * | 2005-06-14 | 2010-11-23 | John Trezza | Remote chip attachment |
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Also Published As
Publication number | Publication date |
---|---|
HK1084236A1 (en) | 2006-07-21 |
JP2006521022A (ja) | 2006-09-14 |
EP1609180B1 (en) | 2013-04-17 |
EP1609180A1 (en) | 2005-12-28 |
CN1791975A (zh) | 2006-06-21 |
SE0300784D0 (sv) | 2003-03-21 |
CA2519893C (en) | 2013-03-12 |
CN1791975B (zh) | 2012-05-09 |
CA2519893A1 (en) | 2004-09-30 |
WO2004084300A1 (en) | 2004-09-30 |
KR20060003333A (ko) | 2006-01-10 |
US7560802B2 (en) | 2009-07-14 |
SE0300784L (sv) | 2004-09-22 |
SE526366C3 (sv) | 2005-10-26 |
DK1609180T3 (da) | 2013-06-24 |
US20070020926A1 (en) | 2007-01-25 |
KR101123002B1 (ko) | 2012-03-16 |
SE526366C2 (sv) | 2005-08-30 |
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