JP2006521022A - 基板中の電気的接続 - Google Patents
基板中の電気的接続 Download PDFInfo
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- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0006—Interconnects
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
Abstract
Description
図7に従来技術である電気的接続の構造を示す(US−6,002,177の図3に対応する)。チップの2つの両面の間に電気的接続を与えるために、シリコンチップ内にホールの穴を開け、前記ホールの内壁を金属化する
標準的なトレンチエッチングがシリコンウエハに施される。ウエハは直径100mm、厚さ500μmである。
したがって、この問題を改善するために、追加で、図2と関連して説明される浅いエッチングが行われる。
図10に完成したビアの長方形の形状を有するアレイの例を示す。
図11は、エッチングがウエハの両面から行われる実施態様によって作られたビアのアレイを示す。
図12にMEMS素子、特に偏光可能なマイクロミラーアレイを作るための概略のプロセス手順を示す。
図13に、MEMS素子を作るためのプロセス手順のさらなる態様を概略的に図示する。
本発明は、図面を参照し以下に説明される。
Claims (24)
- 導電性又は半導電性ウエハの第1(14)(上側)表面と第2(16)(下側)表面との間に絶縁された電気的接続を作る方法であって、
第1表面にトレンチを作成し、
前記トレンチによって規定される前記ウエハの一部分を、前記ウエハからなる周辺材料から完全に分離し、分離された一部分の上側表面及び下側表面を露出させた状態で絶縁性囲いを設けることを含む方法。 - 前記トレンチが、前記ウエハの一部分を囲むがウエハを貫通して伸びていない閉じた環の形状のパターンで規定され;かつ、前記絶縁性囲いが、トレンチ内の絶縁性材料を露出させるために前記下側表面を薄化することによって設けられる請求項1記載の方法。
- 前記表面に少なくとも一つの凹部を得るために、薄化が前記表面に選択的に行われ、少なくとも一つの凹部が前記電気的接続を示す請求項2記載の方法。
- 前記トレンチが、始点及び終点を有する、基板を貫通して伸びる線の形状のパターンで規定され;前記絶縁性囲いが、閉じた環の形状のパターンを規定するために前記第1のトレンチに相補的な第2のトレンチを作成し、ウエハを貫通して伸ばすことによって;かつ、次いで前記第2のトレンチを絶縁性材料で満たすことによって設けられる請求項1記載の方法。
- 前記トレンチが、前記ウエハの一部分を囲むがウエハを貫通して伸びていない閉じた環の形状のパターンで規定され;前記絶縁性囲いが、下側面から第2のトレンチを作成し、前記第1のトレンチと合わせることによって;かつ、次いで第2のトレンチを絶縁性材料によって満たすことによって設けられる請求項1記載の方法。
- トレンチがエッチングプロセスによって作成される前記請求項いずれか記載の方法。
- トレンチがレーザー系加工プロセスによって作成される前記請求項いずれか記載の方法。
- トレンチが放電加工プロセスによって作成される前記請求項いずれか記載の方法。
- 絶縁性材料が前記トレンチ内に導入される前記請求項いずれか記載の方法。
- 前記トレンチが少なくとも部分的に前記絶縁性材料で満たされる請求項9記載の方法。
- ウエハの第1表面と第2表面との間に絶縁された電気的接続を作る方法であって、
適切な導電性又は半導電性材料からなるウエハを用意し、
前記ウエハの少なくとも一つの表面から少なくとも一つのトレンチをエッチングし、前記トレンチは完全に前記ウエハの一部分を囲んでおり、
前記トレンチを絶縁性材料で満たし、それにより前記ウエハを貫通して伸びる絶縁された電気的接続を作成する方法。 - ウエハの第1表面と第2表面との間に絶縁された電気的接続を作る方法であって、
適切な導電性又は半導電性材料からなるウエハを用意し、
前記ウエハの第1表面から少なくとも一つのトレンチをエッチングし、前記トレンチは完全に前記ウエハの一部分を囲んでおり、
前記トレンチを絶縁性材料で満たし、
トレンチ内の絶縁性材料を露出させるために前記ウエハを第2表面から薄くし、それにより前記ウエハを貫通して伸びる絶縁された電気的接続を作成する方法。 - ウエハの第1表面と第2表面との間に絶縁された電気的接続を作る方法であって、
適切な導電性又は半導電性材料からなるウエハを用意し、
前記ウエハの第1表面から少なくとも一つのトレンチをエッチングし、前記トレンチは完全に前記ウエハの一部分を囲んでおり、
前記トレンチを絶縁性材料で満たし、
第2表面からさらに少なくとも一つのトレンチをエッチングし、前記トレンチは、第1表面の前記一部分と一直線に適合する/対応するように、完全に前記ウエハの一部分を囲んでおり、
前記さらなるトレンチを絶縁性材料で満たす方法。 - ウエハの第1表面と第2表面との間に絶縁された電気的接続を作る方法であって、トレンチによって囲まれた材料を選択的にドーピングするために、ドーピング材料をトレンチ内に導入する前記請求項いずれか記載の方法。
- 少なくとも一つのさらなるトレンチ又はホールが、より深いドーピングを可能とするために、ウエハ内の前記トレンチによって囲まれた領域内に設けられる請求項14記載の方法。
- ウエハが、前記キャビティの底部に対応する深さに設けられたエッチングストップ層を含み、それによってトレンチが前記エッチングストップ層によって定められた所定の深さにエッチングされ、かつ、ウエハの薄化が前記エッチングストップ層の除去を含む請求項3記載の方法。
- マイクロエレクトロニック及び/又はマイクロメカニック素子を製造するための出発基板として使用可能な製造物(10)であって、
第1表面(14)及び第2表面(16)を有する半導電性又は導電性の材料からなるウエハ(10);
前記ウエハを貫通して伸びる少なくとも一つの電気的接続部材(12)を含む製造物において、
電気的接続部材(12)が絶縁性材料の限定された層(15)によってウエハからなる周辺材料から絶縁され、
前記電気的接続部材がウエハと同じ材料、すなわち、ウエハ材料から作られていることを特徴とする製造物。 - 前記ウエハが半導体ウエハである請求項17記載の製造物。
- 前記ウエハがシリコンウエハである請求項18記載の製造物。
- 前記ウエハの厚さが200〜5000μm、好ましくは300〜3000μm、最も好ましくは400〜1000μmである請求項16〜19いずれか記載の製造物。
- 絶縁性材料の限定された層の厚さが1〜20μm、通常8〜12μmである請求項16〜20いずれか記載の製造物。
- 電気的接続間のピッチ/中央から中央の距離が10μmより大きく、通常50〜100μmである請求項16〜21いずれか記載の製造物。
- ウエハが基本的に平坦である請求項16〜22いずれか記載の製造物。
- ウエハが、少なくともその一つの面に一つ以上の部分的な凹部(75)を有し、絶縁された電気的接続が前記凹部の底部表面と基本的に同一平面上にある請求項16〜22いずれか記載の製造物。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE0300784-6 | 2003-03-21 | ||
SE0300784A SE526366C3 (sv) | 2003-03-21 | 2003-03-21 | Elektriska anslutningar i substrat |
PCT/SE2004/000439 WO2004084300A1 (en) | 2003-03-21 | 2004-03-22 | Electrical connections in substrates |
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JP2006521022A true JP2006521022A (ja) | 2006-09-14 |
JP4944605B2 JP4944605B2 (ja) | 2012-06-06 |
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JP2006507977A Expired - Lifetime JP4944605B2 (ja) | 2003-03-21 | 2004-03-22 | 基板中の電気的接続 |
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Country | Link |
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US (1) | US7560802B2 (ja) |
EP (1) | EP1609180B1 (ja) |
JP (1) | JP4944605B2 (ja) |
KR (1) | KR101123002B1 (ja) |
CN (1) | CN1791975B (ja) |
CA (1) | CA2519893C (ja) |
DK (1) | DK1609180T3 (ja) |
HK (1) | HK1084236A1 (ja) |
SE (1) | SE526366C3 (ja) |
WO (1) | WO2004084300A1 (ja) |
Cited By (5)
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JP2008541434A (ja) * | 2005-05-04 | 2008-11-20 | アイスモス テクノロジー コーポレイション | ウエハを貫通するビアを有するシリコンウエハ |
WO2010147000A1 (ja) | 2009-06-17 | 2010-12-23 | 浜松ホトニクス株式会社 | 積層配線基板 |
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JP2013140838A (ja) * | 2011-12-28 | 2013-07-18 | Sumitomo Precision Prod Co Ltd | 半導体装置及びその製造方法 |
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Also Published As
Publication number | Publication date |
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EP1609180A1 (en) | 2005-12-28 |
SE526366C3 (sv) | 2005-10-26 |
US7560802B2 (en) | 2009-07-14 |
CN1791975B (zh) | 2012-05-09 |
EP1609180B1 (en) | 2013-04-17 |
SE526366C2 (sv) | 2005-08-30 |
US20070020926A1 (en) | 2007-01-25 |
CN1791975A (zh) | 2006-06-21 |
WO2004084300A1 (en) | 2004-09-30 |
SE0300784L (sv) | 2004-09-22 |
DK1609180T3 (da) | 2013-06-24 |
HK1084236A1 (en) | 2006-07-21 |
KR101123002B1 (ko) | 2012-03-16 |
CA2519893A1 (en) | 2004-09-30 |
CA2519893C (en) | 2013-03-12 |
JP4944605B2 (ja) | 2012-06-06 |
KR20060003333A (ko) | 2006-01-10 |
SE0300784D0 (sv) | 2003-03-21 |
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