JP4812281B2 - 高移動度ヘテロ接合相補型電界効果トランジスタの製造方法 - Google Patents
高移動度ヘテロ接合相補型電界効果トランジスタの製造方法 Download PDFInfo
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Description
11 ヘテロ接合界面
15 Siキャップ層
20 SiGe層
30 Si層
40 Si結晶本体(p導電型Si本体)
40’ p導電型Si本体
51 被覆層
52 ゲート
53 ゲート誘電体
54 絶縁体領域
55 絶縁層
57 マスキング・ステップ
58 n型種の注入ステップ
60 FETデバイスの表面
65 金属学的接合
70 ソース/ドレイン
100 SiGeヘテロ接合ソース/ドレイン・デバイス。
900 プロセッサ
901 チップ
Claims (3)
- 下記ステップを含むP型電界効果トランジスタの製造方法
(1)シリコン・オン・インシュレータ基板を用意するステップ、
(2)前記シリコン・オン・インシュレータ基板の結晶Si層を貫通して該シリコン・オン・インシュレータ基板の埋め込み絶縁層まで延びる少なくとも2つのシャロー・トレンチ分離を設け、該2つのシャロー・トレンチ分離の間の前記シリコン層上にSiGeエピタキシャル層を設け、次いで、前記SiGeエピタキシャル層上にSiエピタキシャル層を設けるステップ、
(3)前記(2)のステップを行ったのち、前記結晶Si層にドーパントを注入して、n型にするステップ、
(4)前記(3)のステップを行ったのち、前記Siエピタキシャル層上にゲート誘電体層を配設するステップ、
(5)前記ゲート誘電体層上にゲート電極を配設し、該ゲート電極の側面及び上面に被覆層を設けるステップ、
(6)前記ゲート誘電体層、Siエピタキシャル層、SiGeエピタキシャル層を通って、前記シリコン・オン・インシュレータ基板の絶縁層に達するまで、ソース/ドレインを形成するための凹部を形成するステップ、及び
(7)前記ソース/ドレインを形成するために、前記凹部内に横方向シーディングによりpドープされたSiGeエピタキシャル層を形成するステップであって、形成されたSiGeエピタキシャル層の上面は、前記ゲート誘電体層と前記Siエピタキシャル層の界面よりも高い、ステップ。 - (8)前記ソース及びドレインのSiGeエピタキシャル層の上に、エピタキシャルSi層を設けるステップをさらに含む、請求項1記載の方法。
- 前記ステップ(2)において、少なくとも3つのシャロー・トレンチ分離を設け、該シャロー・トレンチ分離のうちの隣接する2つの間を前記P型電界効果トランジスタを形成する領域とし、他の隣接する2つの間がN型電界効果トランジスタを形成する領域とするステップをさらに含み、
前記ステップ(3)において、N型電界効果トランジスタを形成する領域の前記結晶Si層にドーパントを注入してp型にするステップをさらに含み、前記ステップ(6)及び(7)を、前記P型電界効果トランジスタを形成する領域でのみ行い、
前記P型電界効果トランジスタをマスクして、前記N型電界効果トランジスタを形成する領域のソース及びドレイン領域にn型ドーパントを注入するステップをさらに含む、請求項1記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/698122 | 2003-10-31 | ||
US10/698,122 US7057216B2 (en) | 2003-10-31 | 2003-10-31 | High mobility heterojunction complementary field effect transistors and methods thereof |
Publications (2)
Publication Number | Publication Date |
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JP2005217391A JP2005217391A (ja) | 2005-08-11 |
JP4812281B2 true JP4812281B2 (ja) | 2011-11-09 |
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Application Number | Title | Priority Date | Filing Date |
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JP2004312192A Expired - Fee Related JP4812281B2 (ja) | 2003-10-31 | 2004-10-27 | 高移動度ヘテロ接合相補型電界効果トランジスタの製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7057216B2 (ja) |
JP (1) | JP4812281B2 (ja) |
KR (1) | KR100633499B1 (ja) |
CN (1) | CN100405611C (ja) |
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CN100405611C (zh) | 2008-07-23 |
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US7368358B2 (en) | 2008-05-06 |
US20060128105A1 (en) | 2006-06-15 |
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