CN100405611C - 高迁移率异质结互补场效应晶体管及其方法 - Google Patents

高迁移率异质结互补场效应晶体管及其方法 Download PDF

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CN100405611C
CN100405611C CNB2004100870097A CN200410087009A CN100405611C CN 100405611 C CN100405611 C CN 100405611C CN B2004100870097 A CNB2004100870097 A CN B2004100870097A CN 200410087009 A CN200410087009 A CN 200410087009A CN 100405611 C CN100405611 C CN 100405611C
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欧阳齐庆
陈向东
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GlobalFoundries Inc
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Abstract

本发明公开了一种高性能场效应器件的结构和制备方法。该MOS结构包括一种导电类型的晶体Si本体，外延地生长在Si本体上作为空穴的埋置沟道的应变的SiGe层，外延地生长在SiGe层作为用于电子的表面沟道的Si层，源和漏，包括外延淀积并具有与Si本体相反的导电极性的应变的SiGe。SiGe源和漏与Si本体形成了异质结和冶金结，其中异质结和冶金结以小于约10nm，优选小于约5nm的公差重合。异质结源/漏为减少短沟道效应的手段。由于增加了压缩应变的SiGe沟道，这些结构对PMOS特别有利。代表性的实施例包括块材和SOI上的CMOS结构。

Description

高迁移率异质结互补场效应晶体管及其方法
技术领域
本发明涉及电子器件及系统。特别涉及场效应器件及制备这种结构的方法，该器件具有基本上与源/漏和器件本体之间的冶金结重合的异质结源/漏。
背景技术
今天的集成电路包括大量的器件。较小器件的关键是增强性能和提高可靠性。随着MOS(金属氧化物半导体场效应器件，在常规的绝缘栅场效应器件中为具有历史性内涵意义的名称)器件不断按比例缩小，技术变得越来越复杂，并且需要新的方法来保持从一代器件到下一代器件预期的性能提高。
在半导体工业中，硅MOS缩放变成主要的挑战。随着器件尺寸缩减到纳米范围以下，常规的技术开始不能减少某些不希望的物理效应。例如，抗穿通或晕圈注入用于降低短沟道效应。然而，由于温度增强了扩散，难以获得突变的掺杂轮廓，并且这些重掺杂的沟道或袋注入区不仅增加了结电容和带与带之间的隧穿，而且降低了沟道中的载流子迁移率。
带隙技术，即将与Si不同能带的新材料引入到Si内在器件设计中提供了重要的附加自由度。这些新材料之中，SiGe合金是其中一个突出成员。通过分子束外延(MBE)或各种化学汽相淀积(CVD)生长高质量的压缩应变SiGe材料将带隙技术的概念引入到成熟的硅技术中。
降低短沟道效应的新方式是在源/本体结具有内建能量势垒。由于异质结势垒的高度不取决于施加的偏置，它可以阻止漏引入的势垒降低(DIBL)。由SiGe异质结提供的带偏置主要在价带中，并且非常适合于使用这种效应用于PEFT。(在下文中，术语PFET和PMOS以及术语NFET和NMOS可以互换使用。)
异质结MOSFET(HJMOSFET)已公开在例如Q.Quyang等人的US.专利6,319,799 B1“High Mobility Heterojunction Transistorand Method”，和Q.Quyang等人的仿真研究“A Novel Si/SiGeHeterjunction pMOSFET with Reduced Short-Channe Effects andEnhanced Drive Current”，IEEE Transactions on Electron Devices，V.47，1943页(2000)中。后一参考文件显示SiGe/Si异质结和掺杂剂冶金结以相对高的精度相互重合，或者在SiGe区内包含p掺杂剂，以便源和体之间的价带偏置。只有在这种精度时异质结才可以有效地用于降低截止状态漏电和短沟道效应。到目前为止，没有方法可以得到异质结和冶金结之间需要的重合，并且没有公开具有这种重合的横向器件结构。
发明内容
本发明介绍了异质结源/漏MOSFET器件，其中PMOS为埋置的SiGe沟道器件，而NMOS为表面硅沟道器件。根据本发明的一个方面，器件的异质结和冶金结在非常小的公差内重合。本发明的另一方面涉及包括通过外延淀积形成异质结源/漏的方法。可以在绝缘体上硅(SOI)或体Si技术中实现新的异质结源/漏MOSFET器件。由于Si和SiGe之间的晶格常数失配，SiGe外延源/漏将压缩应变，由于这种材料中的高空穴迁移率造成PMOS中的空穴电流主要限制到埋置的压缩应变的SiGe沟道，这种PMOS器件可以具有与NMOS器件可能类似的载流能力。高质量的PMOS为构建处理器提供了优良的CMOS电路能力。
本发明提供了一种场效应器件，包括：一种导电类型的晶体Si本体；外延地设置在所述Si本体上的SiGe层；外延地设置在所述SiGe层上的Si层；以及源和漏，包括与Si本体成外延关系的SiGe，并通过SiGe层和Si层相互连接，源和漏具有与Si本体相反的导电类型，每个与Si本体形成了异质结和冶金结，其中异质结和冶金结以小于10nm的公差重合。
本发明还提供了一种PMOS场效应器件包括：n型导电类型的晶体Si本体；外延地设置在n型Si本体上的SiGe层；外延地设置在所述SiGe层上的Si层；以及p型导电类型的源和漏，包括与n型Si本体成外延关系的SiGe，并通过SiGe层和Si层相互连接，源和漏各自与n型Si本体形成了异质结和冶金结，其中异质结和冶金结以小于10nm的公差重合。
本发明还提供了一种制备场效应器件的方法，包括以下步骤：通过第一材料的外延淀积制备源和漏，其中该第一材料与第二材料形成异质结，并且其中第二材料构成了器件的本体；并且，形成本体与源和漏之间的冶金结，其中异质结和冶金结以小于10nm的公差重合，源和漏与本体相比具有相反的导电类型。
本发明提供了一种处理器，包括：至少一个芯片，其中该芯片包括至少一个场效应器件，并且其中至少一个场效应器件包括：一种导电类型的晶体Si本体；外延地设置在所述Si本体上的SiGe层；外延地设置在所述SiGe层上的Si层；以及源和漏，包括与Si本体成外延关系的SiGe，并通过SiGe层和Si层相互连接，源和漏具有与Si本体相反的导电极性，每个与Si本体形成了异质结和冶金结，其中异质结和冶金结以小于10nm的公差重合。
根据以上列出的目标，本发明介绍了具有SiGe异质结源/漏的Si基MOSFET器件，其中异质结和源/漏与Si本体的冶金结以最小的公差重合。
本发明的另一目的是教授了一种用于任何场效应器件处理在异质结和冶金结结构中具有最小公差的异质结源和漏的方法。
本发明的另一目的是教授了处理器，包括含有这种场效应器件的芯片，器件在异质结和冶金结结构中具有最小的公差的异质结源和漏。
附图说明
从下面附带的详细介绍和附图中，本发明的这些和其它特点将变得很显然，其中：
图1示意性地示出了Si基异质结源/漏场器件的示例性实施例；
图2示意性地示出了在互补结构中Si基异质结源/漏场器件的示例性实施例；
图3示出了制备异质结源/漏场器件的示例性实施例中的处理步骤；
图4示出了制备异质结源/漏场器件的备选示例性实施例中的处理步骤；以及
图5示出了含有异质结源/漏场器件的芯片的处理器的符号图。
具体实施方式
图1示意性地示出了Si基异质结源/漏场器件的示例性实施例。每个实施例含有与器件的本体40形成异质结的场效应器件(FET)的源10和漏10特征。对于每个FET，器件具有(至少一个)栅极52。现有技术状态中的导电栅极52由覆盖层51保护，在Si基技术中通常为氧化物和SiN。栅极52通过栅极介质53与器件的其余部分电隔离。FET的共同性质是容性耦合在栅极绝缘体53之间的栅极52控制了源10和漏10之间的器件电流。绝缘区54用于隔离器件。通常通过由SiO2制成的浅沟槽54进行隔离，如图所示。
图1中所示结构的材料属于Si基材料的宽范畴中。在微电子技术中，小型化中进展最好的材料是硅(Si)。Si基材料为具有与Si相同的基本技术含量的多种合金。对于微电子器件一种这种重要的Si基材是硅-锗(Si-Ge)合金。SiGe具有比Si的晶格常数，并随Ge浓度增加而增加。因此，当SiGe外延生长或淀积在Si上时，它处于压缩应变。SiGe的带隙小于Si的。Ge含量越高，SiGe的带隙越小。对于Si-SiGe异质结构，带隙差异几乎完全提供在价带中。在导带中，带不连贯性的几乎可以忽略不计，在与器件本体为异质结关系而具有源和漏的FET中，具有器件小型化的优点。同样，具有由应变的SiGe材料组成的沟道对于载流子迁移率，特别是空穴迁移率具有突出优点。这些优点的原因及具有内容可以在以下公开出版物中找到：Q.Quyang等人的“A Novel Si/SiGe Heterjunction pMOSFET with ReducedShort-Channe Effects and Enhanced Drive Current”，IEEETransactions on Electron Devices，V.47，1943页(2000)。同样具有SiGe异质结源/漏以及SiGe沟道的PMOS公开在Q.Quyang等人的US.专利6,319,799 B1“High Mobility Heterojunction Transistor andMethod”中，这里作为参考引入。
在图1所示的代表性实施例中，器件具有基本上由Si组成的晶体本体40。SiGe层20外延地设置在本体40上。术语“外延地”、“外延”、“epi”等表达了它们的习惯用法：意味着单晶晶格结构支撑界面。通常单晶材料形成了平台，在其上具有通过本领域中已知的几种技术中的一种淀积的具有匹配的晶体特性的另一单晶材料。这样的技术例如为分子束外延(MBE)或各种化学汽相淀积(CVD)。由于SiGe层20和Si本体40之间的晶格常数关系，SiGe层20处于压力应变。这种应变显著增强了空穴迁移率。在SiGe层20的顶部，外延地设置Si层30。该Si层30例如可以作为一种或几种目的，例如：1)用于电子型器件电流的沟道；2)允许生长高质量的栅极介质53，通常为SiO2，可以是与SiN的混合物；或者3)作为保护层以使SiGe层20的污染物最小。
晶体Si本体40和SiGe源和漏10之间毗连的表面与Si本体为外延关系，形成了异质结界面11。术语异质结意味着两个不相类似的材料接触并且在界面11处能带突然不连续。在器件中存在另一重要界面，称做冶金结。如图1的实施例中虚线65所示，其中本体40和源和漏10之间的导电类型改变。本体40和源和漏之间具有相反的导电类型。如果源/漏10为p型，那么本体为n型，反之亦然，如果源/漏10为n型，那么本体为p型。两种类型的掺杂剂，p型，例如硼(B)，n型，例如磷(P)或砷(As)，相互平衡的位置就是本体40和源/漏10之间的冶金结65的位置。为了具体化异质结源/漏的可能的优点，优选异质结11基本上与冶金结重合。由此，本发明的一个方之面提供了制备图1的代表性FET器件实施例的方法，异质结11和冶金结65以小于约10nm的公差重合，并且优选小于约5nm。虽然在图1A、1B和1C中冶金结显示在异质结11的本体40一侧上，但是实际上它同样可以在异质结11的源/漏10一侧。关键在于两者以最小的公差重合。
在显示的所有代表性实施例中，源和漏10以及SiGe外延沟道层20中的Ge浓度在15％到50％的范围内，优选在约20％到40％之间。源/漏10中的SiGe厚度位于给定的Ge浓度的临界厚度之下。定义临界厚度从而超过它时，SiGe将应力释放，并且将形成缺陷和位错。SiGe外延沟道层20的厚度在约5nm和15nm之间。外延Si层30的厚度通常在约5nm和15nm之间。图1A示出了本体为体Si的一个实施例。这种类型的器件为目前微电子器件中最常见的器件。图1B和1C示出了当Si本体40设置在绝缘材料55的顶部上时异质结源/漏FET器件的代表性实施例。这种类型的技术通常称做绝缘体上硅(SOI)技术。绝缘体材料55通常并优选SiO2。图1B示出了本体40具有足够的体积以容纳可移动电荷的SOI实施例。这种SOI器件称做部分耗尽的器件。图1C示出了本体40的体积不足以容纳可移动电荷的SOI实施例。这种SOI器件称做全耗尽的器件。对于图1B和1C中示出了器件，在源和漏10下面存在至少薄的本体层。该本体材料作为籽材料，在其上生长了外延的SiGe源和漏10。在备选的实施例中，对于极薄的全耗尽SOI器件，可以横向地生长源和漏10，从横向的籽晶开始，此时源和漏10将一直穿透到绝缘层55。
图1A示出了Si帽盖层15位于SiGe源和漏10顶上的代表性实施例的附加结构。这种Si帽盖层15的目的主要是有助于与源和漏10较好的电接触。Si帽盖层15的厚度可以较宽松(relax)，通常在约2nm和约3nm之间。该Si帽盖层15通常外延地形成在SiGe源和漏10上，之后立即进行SiGe的外延生长。虽然Si帽盖层15仅图示在图1A中，但是本领域中的技术人员应该理解，它同样可以是其它代表性实施例的一部分。
由于图1C中的全耗尽SOI器件具有浅轮廓，因此有利的是在这种结构中具有所谓的隆起的源/漏10，以减少源/漏串联电阻。FET器件具有良好限定的表面平面，由虚线60示出。该顶表面平面基本上穿过栅极介质53和硅层30之间的界面。对于图1C的全耗尽SOI FET，源10和漏10隆起在顶表面平面之上，得到了需要的优点。
在图1所示的代表性实施例中，Si本体40可以具有n型导电性，即器件为PFET，在这些器件中，价带中异质结不连续的结果，器件空穴流主要限定在SiGe层20中。由于异质结11优选位于本体40和源/漏10之间，但是如果在器件电流的路径中形成了阻挡将很不利，对于SiGe层20优选基本上等于源10和漏10中SiGe的Ge浓度。由于基本上等于Ge浓度，空穴可以没有阻碍地在源10和漏10与SiGe层20之间穿过。
可选地，Si本体40可以具有p型导电性，即器件为NFET。对于这些器件，导带中缺少异质结不连续的结果，器件电子流主要限定在Si层30中。
图2示意性地示出了在互补结构中Si基异质结源/漏场器件的示例性实施例。图2A示出了互补结构中的两个异质结源/漏场器件(CMOS)，即p型MOS和n型MOS。可以得到如下的CMOS：两种类型的器件具有相同特性-即，PMOS和NMOS都具有异质结源/漏，一个器件具有n型导电性的Si本体40，而第二个器件具有p型导电性的Si本体40’。在一个实施例中，PMOS和NMOS具有异质结和冶金结，以小于约10nm的公差重合，优选小于约5nm。可选地，可以得到如下的CMOS结构：PMOS和NMOS都具有SiGe异质结源/漏，但是仅PMOS器件具有大致的重合，异质结和冶金结之间的公差小于约10nm，优选小于约5nm的公差。
图2B示出了仅PMOS器件具有异质结和冶金结之间在公差小于约10nm，优选小于约5nm之内大致重合的异质结源/漏10。然而此时，NMOS器件在源70和漏70中没有SiGe，尽管它具有SiGe层20和Si层30。从NMOS器件中省略源/漏10具有一些益处。例如，由通常约500-600℃的外延SiGe生长温度冷却之后，压缩应变的外延SiGe源/漏将在栅极边缘附近的硅本体中产生一些压缩应力。这使得栅极边缘附近的SiGe更加压缩应变。这种额外的压缩应变实际上对PMOS很有利，导致p沟道中更高的空穴迁移率。然而，与体硅相比，NMOS的Si的n沟道中的压缩应变降低了电子迁移率。对于更短的栅极长度，效应变得更明显。因此，由于具有异质结源/漏10的PMOS器件的强度，在NMOS具有SiGe层20和Si层30的常规的源和漏70的图2B中，CMOS的该代表性实施例具有优异的性能。在另一代表性实施例中，PMOS器件具有异质结源/漏10，和按公差小于约10nm并优选小于约5nm而基本上重合的异质结和冶金结，可以与任何常规的NMOS器件成对形成CMOS结构。
具有异质结源/漏和基本上重合的异质结和冶金结的PFET器件的一个优点是除了由n型Si本体40和p型SiGe源/漏10之间的p/n结而固有的电势之外，在应变的SiGe/Si界面11处的带偏置提供了对于空穴的势垒，它不随漏极偏压改变，由此对于PFET可以显著地降低漏引入的势垒下降和截止状态泄露电流。
通过根据晶面和晶向定向器件可以进一步增强由空穴迁移率增加获得的PFET的优点。由于空穴迁移率已知在(110)表面上通常较高，并且电子迁移率已知在(100)表面上通常较高，因此CMOS具有混合的晶向结构，由此PFET位于(110)表面上，NFET位于(100)表面上。一般来说，有利的是将PMOS和NMOS器件取向在它们的表面平面60上(图1C)，该表面平面实质上位于主晶向(100)、(110)以及(111)的任一个中。此外，在典型的(100)晶面表面上，沟道可以设置得电流沿<100>和/或<110>方向，对于空穴和电子都具有较高的载流子迁移率。局部应力与沟道方向和晶向相关。
具有应变的SiGe源/漏的PFET和NFET的优点有很多，现在列举如下。由于与Si相比SiGe中的B和P的溶解度较高，因此由源/漏导致的那部分器件串联电阻降低。接下来，由于SiGe的带隙较小，因此接触电阻可以更小。而且，在SOI实施例中，由于SiGe内较窄带隙的势垒高度下降，由于漏附近的碰撞电离产生的热载流子会扩散穿过势垒进入源内，因此浮体效应降低。该效应会发生在PFET和NFET中。同样，源/漏击穿(BVds)可以显著改善。对于超薄全耗尽的SOI，可以使用图1C的隆起的SiGe源/漏。可以保持SiGe中的应变，只要它的厚度在临界厚度之下。
本发明的一个方面提供了通过外延淀积源/漏材料制备用于FET的异质结源/漏。例如通过分子束外延(MBE)或多种类型的化学汽相淀积(CVD)，这种外延淀积可以获得需要的材料纯度、晶体质量以及控制。
通过外延淀积制备源/漏的方法不限于Si、SiGe材料系，而是可以应用于多种器件，例如III-V半导体族。由此，通过外延淀积与第二材料形成异质结的第一材料通常形成了源和漏，第二材料构成了FET器件的本体。如果有利，例如对于图1的SiGe源/漏PMOS，可以进一步包括在源和漏之间提供沟道的制造步骤，由此沟道实质上由第一材料，即源/漏的材料组成。可选地，或者与第一材料沟道结合，可以进行在源和漏之间提供沟道的步骤，源/漏实质上由第二材料，即与器件本体的相同。而且，在MBE和/或CVD中提供的精确控制允许掺杂源和漏，由此本体提供有一种导电类型，源和漏提供有相反的导电类型，形成了本体与源和漏之间的冶金结，而且具有小公差重合的异质结和冶金结，在现有的FET的技术中，小公差需要小于约10nm，优选小于约5nm。
图3和4示出了异质结源/漏场器件的示例性实施例中的工艺步骤。SiGe异质结源/漏场器件的CMOS工艺可以依照现有技术中公知的CMOS工艺中许多成熟的步骤。仅讨论对于异质结源/漏场器件独特的那些步骤并显示在图3和4中。图3和4示出了未全耗尽的SOI器件的示例性实施例的工艺步骤，如同在图1B上。然而，在其它的示例性实施例中，例如体器件，或者全耗尽的SOI器件，异质结源/漏场器件特定的步骤是相同的。
图3A示出了在设置在绝缘材料55上的Si本体40中进行浅沟槽54隔离之后的制备，已淀积了SiGe外延层20和Si外延层30。可以选择隔离和外延生长的顺序以适合特殊需要的工艺顺序。可以在制备浅沟槽隔离54之前或之后生长外延层20和30。
图3B示出了进行了本领域中公知的几个工艺步骤之后的工艺。CMOS阱注入和阈值调节注入已经进行，结果Si本体成为两种导电类型，即n和p型40和40’。已经生长了栅介质53，典型地为氧化物。淀积并构图栅52，并形成栅覆盖/隔离层51。图3C表示源/漏区已经被凹进，以得到用于随后淀积SiGe材料的空间。这样的凹进/蚀刻可以采用现有技术已知的技术来进行，如反应离子蚀刻，和/或各种湿刻。
图3D表示向凹陷的源/漏区中原位p掺杂SiGe合金的选择性外延。p掺杂的外延进入到PMOS和NMOS中，在两个器件中产生相同的源/漏10。SiGe合金的原位掺杂淀积使得可以充分控制掺杂剖面，从而异质结和冶金结之间基本上重合。在示例的实施方式中，这种源和漏的选择性外延可以通过采用SiH4、Si2H4或GeH4前体在大约400-650℃的温度范围内、优选大约550℃的超高真空化学气相淀积(UHV-CVD)来进行。为了控制冶金结的位置，可以在外延期间采用添加的B2H5对膜原位硼掺杂。
该图也代表性地示出了在SiGe源和漏10的顶部产生外延Si帽盖层15的帽盖形成步骤。Si帽盖层1的外延在源和漏的SiGe外延之后。这样的Si帽盖层便于接触到器件。Si帽盖层的厚度可以较宽松，典型地在2nm和30nm之间。尽管淀积这种Si帽盖层15步骤仅显示在图3D中，本领域中的技术人员应该理解，这同样仅为其它代表性实施例的制造顺序的一部分。
图3E示出了在这种优选实施例中的最终步骤。在掩蔽PMOS 57时，例如用磷或砷的n型物质注入NMOS源/漏区58。注入剂量高足以超越p掺杂剂并将NMOS的SiGe源/漏转变成n型10’材料，将Si帽盖层转变成重掺杂的n掺杂15’。通常用快速热退火激活该注入58，能较精确地控制冶金结位置。在示例性实施例中，快速热退火调节可以约1050-1100℃，小于10秒钟。或者，可以使用激光退火或快速退火以获得更短的退火时间。
可以改变外延淀积和源/漏掺杂步骤。如果需要代替p掺杂的SiGe外延，那么对于PMOS和NMOS器件，需要进行未掺杂的SiGe外延和注入并激活源/漏。对于一些情况，甚至可以使用外延淀积。对于本领域中的普通技术人员，显然可以进一步改变这些步骤。
图4示出了制备异质结源/漏场器件的备选示例性实施例中的处理步骤。由于以上所述SiGe异质结源/漏场器件的主要收益者是PFET器件，可以和NFET一起省略异质结，以便避免由SiGe源/漏产生的应变，如上参考图2B介绍的。图4A示出了工艺的中间阶段，所有的步骤都在实施图3所示的凹进源/漏之前，SiGe外延层20和Si外延层30存在于NMOS。然而仅对PMOS进行源/漏凹进和SiGe源/漏外延步骤。这导致图4A所示的情况，PMOS具有SiGe外延源/漏10，NMOS没有源和漏。图4B中所示的下一步骤类似于图3E中的一个。PMOS被掩蔽57，注入NFET的源/漏58。本实施例与图3E的实施例之间的差异为注入58仅进入Si本体40’内，得到常见的源/漏70，Si本体40’没有形成异质结。
图5示出了含有异质结源/漏场器件的芯片的处理器的符号图。这种处理器900具有至少一个芯片901，含有至少一个场效应器件100，具有SiGe异质结源/漏和按小于约10nm并且优选约5nm公差重合的异质结和冶金结。处理器900可以是受益于SiGe异质结源/漏器件的任何处理器。这些器件形成了一个或多个芯片901上处理器的一部分。在代表性实施例中，用SOI技术制备这些SiGe异质结源/漏场器件100。用SiGe异质结源/漏场器件制备的处理的代表性实施例为数字处理器，通常位于计算机的中央处理器群中；混合的数字/模拟处理器，显著受益于p型SiGe异质结源/漏场效应器件中载流子的高迁移率；以及一般来说任何通信处理器，例如连接存储器到处理器的模块、缩放刻模机、雷达系统、高性能的可视电话、游戏模块等。
根据以上教授，可以对本发明做出许多修改和变形，并且对本领域中的技术人员来说是显而易见的。本发明的范围由权利要求书限定。

Claims (37)

1.一种场效应器件，包括：
一种导电类型的晶体Si本体；
外延地设置在所述Si本体上的SiGe层；
外延地设置在所述SiGe层上的Si层；以及
源和漏，包括与Si本体成外延关系的SiGe，并通过SiGe层和Si层相互连接，源和漏具有与Si本体相反的导电类型，每个与Si本体形成了异质结和冶金结，其中异质结和冶金结以小于10nm的公差重合。
2.根据权利要求1的器件，其中公差小于5nm。
3.根据权利要求1的器件，其中Si本体设置在绝缘层的顶部上。
4.根据权利要求3的器件，其中绝缘层是SiO2。
5.根据权利要求1的器件，其中Si本体导电类型为n型，并且其中空穴器件电流主要限制在SiGe层中。
6.根据权利要求5的器件，其中空穴器件电流沿着<100>或<110>晶向中的一个取向。
7.根据权利要求1的器件，其中Si本体导电类型为p型，并且其中电子器件电流主要限制在Si层中。
8.根据权利要求1的器件，其中SiGe层和源和漏中的SiGe压缩应变。
9.根据权利要求1的器件，其中SiGe层厚度在5nm和15nm之间。
10.根据权利要求1的器件，其中SiGe层具有等于源和漏中的SiGe中Ge浓度的Ge浓度。
11.根据权利要求10的器件，其中SiGe层中的Ge浓度在15％和50％之间。
12.根据权利要求1的器件，其中器件具有顶部表面平面，并且其中源和漏隆起在顶部表面平面之上。
13.根据权利要求1的器件，其中器件具有位于(100)、(110)或(111)晶面之一中的顶部表面平面。
14.根据权利要求1的器件，其中源和漏进一步包括设置在应变的SiGe顶部上的外延Si帽盖层，其中Si帽盖层位于2nm和30nm厚度之间。
15.根据权利要求1的器件，其中Si本体导电类型为n型，器件以互补电路结构与场效应器件连接，该场效应器件包括：
p型导电类型的晶体Si本体；
外延地设置在p型Si本体上的SiGe层；
外延地设置在所述SiGe层上的Si层；以及
n型导电类型的源和漏，包括与Si本体成外延关系的SiGe，并通过SiGe层和Si层相互连接，源和漏各自与Si本体形成了异质结和冶金结，其中异质结和冶金结以小于10nm的公差重合。
16.根据权利要求1的器件，其中Si本体导电类型为n型，器件以互补电路结构与场效应器件连接，该场效应器件包括：
p型导电类型的晶体Si本体；
外延地设置在p型Si本体上的SiGe层；
外延地设置在所述SiGe层上的Si层；以及
n型导电类型的源和漏，包括与p型Si本体成外延关系的SiGe，并通过SiGe层和Si层相互连接。
17.根据权利要求1的器件，其中Si本体导电类型为n型，器件以互补电路结构与场效应器件连接，该场效应器件包括：
p型导电类型的晶体Si本体；
外延地设置在p型Si本体上的SiGe层；
外延地设置在所述SiGe层上的Si层；以及
通过SiGe层和Si层相互连接的n型导电类型的源和漏。
18.根据权利要求1的器件，其中Si本体导电类型为n型，所述器件以互补电路结构与NMOS器件连接。
19.一种PMOS场效应器件包括：
n型导电类型的晶体Si本体；
外延地设置在n型Si本体上的SiGe层；
外延地设置在所述SiGe层上的Si层；以及
p型导电类型的源和漏，包括与n型Si本体成外延关系的SiGe，并通过SiGe层和Si层相互连接，源和漏各自与n型Si本体形成了异质结和冶金结，其中异质结和冶金结以小于10nm的公差重合。
20.根据权利要求19的器件，其中公差小于5nm。
21.根据权利要求19的器件，其中Si本体设置在绝缘层的顶上。
22.根据权利要求21的器件，其中绝缘层是SiO2。
23.根据权利要求19的器件，其中SiGe层厚度在5nm和15nm之间。
24.根据权利要求19的器件，其中SiGe层中的Ge浓度在15％和50％之间。
25.根据权利要求24的器件，其中SiGe层的Ge浓度等于源和漏中的SiGe中Ge浓度。
26.一种制备场效应器件的方法，包括以下步骤：
通过第一材料的外延淀积制备源和漏，其中该第一材料与第二材料形成异质结，并且其中第二材料构成了器件的本体；并且，
形成本体与源和漏之间的冶金结，其中异质结和冶金结以小于10nm的公差重合，源和漏与本体相比具有相反的导电类型。
27.根据权利要求26的方法，还包括以下步骤：
提供源和漏之间的沟道，其中沟道由第一材料组成。
28.根据权利要求26的方法，还包括以下步骤：
提供源和漏之间的沟道，其中沟道由第二材料组成。
29.根据权利要求26的方法，其中本体导电类型为选自n型或p型中的一种。
30.根据权利要求27的方法，其中第一材料选为SiGe，第二材料选为Si。
31.根据权利要求30的方法，其中本体选择为绝缘体上的Si层。
32.根据权利要求30的方法，其中在外延淀积中，将SiGe选择为未掺杂状态或p掺杂状态中的一种。
33.根据权利要求30的方法，其中在外延淀积中，将SiGe选择为具有15％和50％之间的Ge浓度。
34.根据权利要求30的方法，其中SiGe沟道选择为厚度在5nm和15nm之间。
35.根据权利要求26的方法，还包括用具有2nm和30nm之间厚度的第二材料的外延层对第一材料形成帽盖的步骤。
36.根据权利要求26的方法，其中器件具有顶部表面平面，并且源和漏制作成高于顶部表面平面。
37.一种处理器，包括：
至少一个芯片，其中该芯片包括至少一个场效应器件，并且其中至少一个场效应器件包括：
一种导电类型的晶体Si本体；
外延地设置在所述Si本体上的SiGe层；
外延地设置在所述SiGe层上的Si层；以及
源和漏，包括与Si本体成外延关系的SiGe，并通过SiGe层和Si层相互连接，源和漏具有与Si本体相反的导电极性，每个与Si本体形成了异质结和冶金结，其中异质结和冶金结以小于10nm的公差重合。
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