JP4693428B2 - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

Info

Publication number
JP4693428B2
JP4693428B2 JP2005020111A JP2005020111A JP4693428B2 JP 4693428 B2 JP4693428 B2 JP 4693428B2 JP 2005020111 A JP2005020111 A JP 2005020111A JP 2005020111 A JP2005020111 A JP 2005020111A JP 4693428 B2 JP4693428 B2 JP 4693428B2
Authority
JP
Japan
Prior art keywords
metal
integrated circuit
semiconductor integrated
wiring
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005020111A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006210607A (ja
JP2006210607A5 (enExample
Inventor
正 中村
清彦 榊原
浩 滝川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2005020111A priority Critical patent/JP4693428B2/ja
Priority to US11/328,194 priority patent/US7358548B2/en
Priority to TW095100837A priority patent/TW200644161A/zh
Priority to KR1020060008212A priority patent/KR20060086880A/ko
Priority to CNB2006100024302A priority patent/CN100536133C/zh
Publication of JP2006210607A publication Critical patent/JP2006210607A/ja
Publication of JP2006210607A5 publication Critical patent/JP2006210607A5/ja
Priority to US12/071,624 priority patent/US20080149966A1/en
Application granted granted Critical
Publication of JP4693428B2 publication Critical patent/JP4693428B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/998—Input and output buffer/driver structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Microcomputers (AREA)
  • Dram (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2005020111A 2005-01-27 2005-01-27 半導体集積回路 Expired - Fee Related JP4693428B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2005020111A JP4693428B2 (ja) 2005-01-27 2005-01-27 半導体集積回路
US11/328,194 US7358548B2 (en) 2005-01-27 2006-01-10 Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner
TW095100837A TW200644161A (en) 2005-01-27 2006-01-10 Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner
KR1020060008212A KR20060086880A (ko) 2005-01-27 2006-01-26 반도체 집적 회로
CNB2006100024302A CN100536133C (zh) 2005-01-27 2006-01-27 具有集中地配置了缓冲器或保护电路的布局的半导体集成电路
US12/071,624 US20080149966A1 (en) 2005-01-27 2008-02-25 Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005020111A JP4693428B2 (ja) 2005-01-27 2005-01-27 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2006210607A JP2006210607A (ja) 2006-08-10
JP2006210607A5 JP2006210607A5 (enExample) 2008-02-14
JP4693428B2 true JP4693428B2 (ja) 2011-06-01

Family

ID=36695849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005020111A Expired - Fee Related JP4693428B2 (ja) 2005-01-27 2005-01-27 半導体集積回路

Country Status (5)

Country Link
US (2) US7358548B2 (enExample)
JP (1) JP4693428B2 (enExample)
KR (1) KR20060086880A (enExample)
CN (1) CN100536133C (enExample)
TW (1) TW200644161A (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4693428B2 (ja) * 2005-01-27 2011-06-01 ルネサスエレクトロニクス株式会社 半導体集積回路
TWI381385B (zh) * 2007-05-04 2013-01-01 Macronix Int Co Ltd 具有嵌入式多類型記憶體的記憶體結構
KR100798896B1 (ko) * 2007-06-07 2008-01-29 주식회사 실리콘웍스 반도체 칩의 패드 배치 구조
US8138787B2 (en) * 2008-07-13 2012-03-20 Altera Corporation Apparatus and method for input/output module that optimizes frequency performance in a circuit
JP5419431B2 (ja) * 2008-11-28 2014-02-19 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP5503208B2 (ja) 2009-07-24 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置
JP2017135308A (ja) * 2016-01-29 2017-08-03 セイコーエプソン株式会社 半導体集積回路装置及びそのレイアウト設計方法、並びに、電子機器
US11367478B2 (en) 2020-01-14 2022-06-21 Changxin Memory Technologies, Inc. Integrated circuit structure and memory
WO2021143050A1 (zh) * 2020-01-14 2021-07-22 长鑫存储技术有限公司 集成电路结构和存储器

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4454591A (en) * 1980-05-29 1984-06-12 Texas Instruments Incorporated Interface system for bus line control
US5300796A (en) * 1988-06-29 1994-04-05 Hitachi, Ltd. Semiconductor device having an internal cell array region and a peripheral region surrounding the internal cell array for providing input/output basic cells
JPH08125130A (ja) 1994-10-26 1996-05-17 Matsushita Electric Ind Co Ltd 半導体集積回路
JPH09232437A (ja) * 1996-02-27 1997-09-05 Hitachi Ltd 半導体集積回路装置およびそれを用いたコンピュータシステム
JP3380465B2 (ja) * 1998-06-29 2003-02-24 松下電器産業株式会社 半導体装置
JP3374967B2 (ja) * 1998-10-26 2003-02-10 日本電気株式会社 半導体集積回路
JP2002050742A (ja) * 2000-07-31 2002-02-15 Nec Corp 半導体装置およびその製造方法
JP4904619B2 (ja) * 2000-11-29 2012-03-28 富士通セミコンダクター株式会社 半導体装置
US6502231B1 (en) * 2001-05-31 2002-12-31 Applied Micro Circuits Corporation Integrated circuit template cell system and method
JP2003158195A (ja) * 2001-11-20 2003-05-30 Hitachi Ltd 半導体集積回路装置の製造方法
DE10220923B4 (de) * 2002-05-10 2006-10-26 Infineon Technologies Ag Verfahren zur Herstellung eines nicht-flüchtigen Flash-Halbleiterspeichers
US6735108B2 (en) * 2002-07-08 2004-05-11 Micron Technology, Inc. ROM embedded DRAM with anti-fuse programming
US7003750B2 (en) * 2002-08-01 2006-02-21 Sun Microsystems, Inc. Topology based wire shielding generation
JP4190865B2 (ja) * 2002-11-11 2008-12-03 Ｎｅｃエレクトロニクス株式会社 半導体メモリ
JP4624660B2 (ja) * 2003-10-09 2011-02-02 ルネサスエレクトロニクス株式会社 半導体装置
US7006370B1 (en) * 2003-11-18 2006-02-28 Lsi Logic Corporation Memory cell architecture
JP4693428B2 (ja) * 2005-01-27 2011-06-01 ルネサスエレクトロニクス株式会社 半導体集積回路

Also Published As

Publication number Publication date
KR20060086880A (ko) 2006-08-01
US20060163615A1 (en) 2006-07-27
JP2006210607A (ja) 2006-08-10
CN1819196A (zh) 2006-08-16
US7358548B2 (en) 2008-04-15
CN100536133C (zh) 2009-09-02
US20080149966A1 (en) 2008-06-26
TW200644161A (en) 2006-12-16

Similar Documents

Publication Publication Date Title
JP5730607B2 (ja) ３次元半導体装置の配線構造体
US20080149966A1 (en) Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner
JP2008182058A (ja) 半導体装置および半導体装置形成方法
JP3967199B2 (ja) 半導体装置及びその製造方法
JP4492940B2 (ja) 半導体装置
KR20200038138A (ko) 반도체 장치 및 그 제조방법
CN113725219B (zh) 三维存储器装置及其制造方法
KR100632656B1 (ko) 플래쉬 메모리소자의 비트라인 형성방법
JP3789266B2 (ja) 半導体装置レイアウト方法及び半導体装置をレイアウトするためのプログラムを記録した記録媒体
JP2006108329A (ja) 半導体装置
JP4829333B2 (ja) 半導体記憶装置
JP3599970B2 (ja) 半導体記憶装置
CN115483223B (zh) 半导体存储器装置和半导体存储器装置的制造方法
JP2000311964A (ja) 半導体装置
KR20060060596A (ko) 반도체 기억 장치
CN113130499B (zh) 半导体存储器装置及其制造方法
JP2010225880A (ja) 半導体装置及びその製造方法
US20240008261A1 (en) Method for manufacturing a semiconductor structure having air gap
JP4698427B2 (ja) 半導体装置の製造方法
JP2006080253A (ja) 半導体記憶装置
US12058848B2 (en) Semiconductor structure having air gap
TWI871590B (zh) 具有氣隙的半導體結構
JP2004288786A (ja) 半導体装置
US20250386511A1 (en) Semiconductor device, electronic system including the same, and method for manufacturing the same
TWI854484B (zh) 半導體記憶裝置、及半導體裝置之製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071219

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071219

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100526

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101117

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101130

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110118

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110215

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110222

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140304

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4693428

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees