TW200644161A - Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner - Google Patents

Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner

Info

Publication number
TW200644161A
TW200644161A TW095100837A TW95100837A TW200644161A TW 200644161 A TW200644161 A TW 200644161A TW 095100837 A TW095100837 A TW 095100837A TW 95100837 A TW95100837 A TW 95100837A TW 200644161 A TW200644161 A TW 200644161A
Authority
TW
Taiwan
Prior art keywords
integrated circuit
semiconductor integrated
buffers
concentrated manner
region
Prior art date
Application number
TW095100837A
Other languages
English (en)
Chinese (zh)
Inventor
Tadashi Nakamura
Kiyohiko Sakakibara
Yutaka Takikawa
Original Assignee
Renesas Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Tech Corp filed Critical Renesas Tech Corp
Publication of TW200644161A publication Critical patent/TW200644161A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/998—Input and output buffer/driver structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Microcomputers (AREA)
TW095100837A 2005-01-27 2006-01-10 Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner TW200644161A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005020111A JP4693428B2 (ja) 2005-01-27 2005-01-27 半導体集積回路

Publications (1)

Publication Number Publication Date
TW200644161A true TW200644161A (en) 2006-12-16

Family

ID=36695849

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095100837A TW200644161A (en) 2005-01-27 2006-01-10 Semiconductor integrated circuit having layout in which buffers or protection circuits are arranged in concentrated manner

Country Status (5)

Country Link
US (2) US7358548B2 (enExample)
JP (1) JP4693428B2 (enExample)
KR (1) KR20060086880A (enExample)
CN (1) CN100536133C (enExample)
TW (1) TW200644161A (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4693428B2 (ja) * 2005-01-27 2011-06-01 ルネサスエレクトロニクス株式会社 半導体集積回路
TWI381385B (zh) * 2007-05-04 2013-01-01 Macronix Int Co Ltd 具有嵌入式多類型記憶體的記憶體結構
KR100798896B1 (ko) * 2007-06-07 2008-01-29 주식회사 실리콘웍스 반도체 칩의 패드 배치 구조
US8138787B2 (en) * 2008-07-13 2012-03-20 Altera Corporation Apparatus and method for input/output module that optimizes frequency performance in a circuit
JP5419431B2 (ja) * 2008-11-28 2014-02-19 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP5503208B2 (ja) 2009-07-24 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置
JP2017135308A (ja) * 2016-01-29 2017-08-03 セイコーエプソン株式会社 半導体集積回路装置及びそのレイアウト設計方法、並びに、電子機器
WO2021143050A1 (zh) * 2020-01-14 2021-07-22 长鑫存储技术有限公司 集成电路结构和存储器
US11367478B2 (en) 2020-01-14 2022-06-21 Changxin Memory Technologies, Inc. Integrated circuit structure and memory

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4454591A (en) * 1980-05-29 1984-06-12 Texas Instruments Incorporated Interface system for bus line control
US5300796A (en) * 1988-06-29 1994-04-05 Hitachi, Ltd. Semiconductor device having an internal cell array region and a peripheral region surrounding the internal cell array for providing input/output basic cells
JPH08125130A (ja) 1994-10-26 1996-05-17 Matsushita Electric Ind Co Ltd 半導体集積回路
JPH09232437A (ja) * 1996-02-27 1997-09-05 Hitachi Ltd 半導体集積回路装置およびそれを用いたコンピュータシステム
JP3380465B2 (ja) * 1998-06-29 2003-02-24 松下電器産業株式会社 半導体装置
JP3374967B2 (ja) * 1998-10-26 2003-02-10 日本電気株式会社 半導体集積回路
JP2002050742A (ja) * 2000-07-31 2002-02-15 Nec Corp 半導体装置およびその製造方法
JP4904619B2 (ja) * 2000-11-29 2012-03-28 富士通セミコンダクター株式会社 半導体装置
US6502231B1 (en) * 2001-05-31 2002-12-31 Applied Micro Circuits Corporation Integrated circuit template cell system and method
JP2003158195A (ja) * 2001-11-20 2003-05-30 Hitachi Ltd 半導体集積回路装置の製造方法
DE10220923B4 (de) * 2002-05-10 2006-10-26 Infineon Technologies Ag Verfahren zur Herstellung eines nicht-flüchtigen Flash-Halbleiterspeichers
US6735108B2 (en) * 2002-07-08 2004-05-11 Micron Technology, Inc. ROM embedded DRAM with anti-fuse programming
US7003750B2 (en) * 2002-08-01 2006-02-21 Sun Microsystems, Inc. Topology based wire shielding generation
JP4190865B2 (ja) * 2002-11-11 2008-12-03 Ｎｅｃエレクトロニクス株式会社 半導体メモリ
JP4624660B2 (ja) * 2003-10-09 2011-02-02 ルネサスエレクトロニクス株式会社 半導体装置
US7006370B1 (en) * 2003-11-18 2006-02-28 Lsi Logic Corporation Memory cell architecture
JP4693428B2 (ja) * 2005-01-27 2011-06-01 ルネサスエレクトロニクス株式会社 半導体集積回路

Also Published As

Publication number Publication date
JP4693428B2 (ja) 2011-06-01
CN100536133C (zh) 2009-09-02
US7358548B2 (en) 2008-04-15
CN1819196A (zh) 2006-08-16
KR20060086880A (ko) 2006-08-01
JP2006210607A (ja) 2006-08-10
US20080149966A1 (en) 2008-06-26
US20060163615A1 (en) 2006-07-27

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