DE60110227D1 - Integrierte schaltung mit flash - Google Patents

Integrierte schaltung mit flash

Info

Publication number
DE60110227D1
DE60110227D1 DE60110227T DE60110227T DE60110227D1 DE 60110227 D1 DE60110227 D1 DE 60110227D1 DE 60110227 T DE60110227 T DE 60110227T DE 60110227 T DE60110227 T DE 60110227T DE 60110227 D1 DE60110227 D1 DE 60110227D1
Authority
DE
Germany
Prior art keywords
flash
microprocessor
width
bus
flash memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60110227T
Other languages
English (en)
Other versions
DE60110227T2 (de
Inventor
Hans-Joachim Gelke
Stefan Koch
Steffen Gappisch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE60110227D1 publication Critical patent/DE60110227D1/de
Application granted granted Critical
Publication of DE60110227T2 publication Critical patent/DE60110227T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Microcomputers (AREA)
  • Bipolar Transistors (AREA)
  • Memory System (AREA)
  • Bus Control (AREA)
DE60110227T 2000-06-27 2001-06-20 Integrierte schaltung mit flash Expired - Lifetime DE60110227T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP00113609 2000-06-27
EP00113609 2000-06-27
PCT/EP2001/007009 WO2002001375A1 (en) 2000-06-27 2001-06-20 Integrated circuit with flash

Publications (2)

Publication Number Publication Date
DE60110227D1 true DE60110227D1 (de) 2005-05-25
DE60110227T2 DE60110227T2 (de) 2006-02-09

Family

ID=8169085

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60110227T Expired - Lifetime DE60110227T2 (de) 2000-06-27 2001-06-20 Integrierte schaltung mit flash

Country Status (7)

Country Link
US (1) US6735661B2 (de)
EP (1) EP1297434B1 (de)
JP (2) JP5076133B2 (de)
KR (1) KR100814247B1 (de)
AT (1) ATE293810T1 (de)
DE (1) DE60110227T2 (de)
WO (1) WO2002001375A1 (de)

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US7882299B2 (en) 2004-12-21 2011-02-01 Sandisk Corporation System and method for use of on-chip non-volatile memory write cache
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US8415978B2 (en) * 2008-12-29 2013-04-09 Stmicroelectronics S.R.L. State machine for generating a pulse width modulation (PWM) waveform
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US8707104B1 (en) 2011-09-06 2014-04-22 Western Digital Technologies, Inc. Systems and methods for error injection in data storage systems
US9195530B1 (en) 2011-09-06 2015-11-24 Western Digital Technologies, Inc. Systems and methods for improved data management in data storage systems
US8713357B1 (en) 2011-09-06 2014-04-29 Western Digital Technologies, Inc. Systems and methods for detailed error reporting in data storage systems
US8700834B2 (en) 2011-09-06 2014-04-15 Western Digital Technologies, Inc. Systems and methods for an enhanced controller architecture in data storage systems
US9053008B1 (en) 2012-03-26 2015-06-09 Western Digital Technologies, Inc. Systems and methods for providing inline parameter service in data storage devices
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US10031869B1 (en) 2014-03-28 2018-07-24 Adesto Technologies Corporation Cached memory structure and operation
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Also Published As

Publication number Publication date
ATE293810T1 (de) 2005-05-15
JP2012198935A (ja) 2012-10-18
KR20030009290A (ko) 2003-01-29
JP2004502240A (ja) 2004-01-22
US20020013874A1 (en) 2002-01-31
EP1297434A1 (de) 2003-04-02
DE60110227T2 (de) 2006-02-09
KR100814247B1 (ko) 2008-03-17
WO2002001375A1 (en) 2002-01-03
JP5076133B2 (ja) 2012-11-21
US6735661B2 (en) 2004-05-11
EP1297434B1 (de) 2005-04-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL