KR20030009290A - 집적 회로 - Google Patents
집적 회로 Download PDFInfo
- Publication number
- KR20030009290A KR20030009290A KR1020027002472A KR20027002472A KR20030009290A KR 20030009290 A KR20030009290 A KR 20030009290A KR 1020027002472 A KR1020027002472 A KR 1020027002472A KR 20027002472 A KR20027002472 A KR 20027002472A KR 20030009290 A KR20030009290 A KR 20030009290A
- Authority
- KR
- South Korea
- Prior art keywords
- microprocessor
- bus
- flash
- data
- flash memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
- G06F13/4018—Coupling between buses with data restructuring with data-width conversion
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Microcomputers (AREA)
- Bipolar Transistors (AREA)
- Memory System (AREA)
- Bus Control (AREA)
Abstract
Description
Claims (10)
- 적어도 하나의 마이크로프로세서 및 적어도 하나의 메모리를 가지는 집적 회로에 있어서,상기 메모리는 전용 플래쉬 버스(2)에 의해서 상기 마이크로프로세서에 동작상 연결되는 비휘발성 또는 플래쉬 메모리(1)이며,상기 전용 플래쉬 버스(2)는 특히 상기 마이크로프로세서(3) 또는 상기 마이크로프로세서의 데이터 버스(8)의 제 2 폭 n의 정수배 보다 각기 큰 제 1 폭 m을 가지는 집적 회로.
- 제 1 항에 있어서,상기 플래쉬 버스(2)와 상기 마이크로프로세서(3)를, 바람직하게는 상기 마이크프로세서의 데이터 버스(8)를 경유하여 접속하여 폭의 변환을 수행하는 제 1 수단, 특히 다수의 중간 저장 레지스터(4,28)를 더 포함하는 집적 회로.
- 제 2 항에 있어서,상기 제 1 수단은 중간 저장 레지스터(4,28)의 뱅크이며, 상기 뱅크 내로 상기 플래쉬 메모리(1)로부터 패치(fetch)되는 상기 m 비트 폭의 데이터가 저장되는집적 회로.
- 제 2 항 또는 제 3 항에 있어서,상기 프로세서 데이터 버스는 n = 32 비트 폭이며,상기 플래쉬 버스는 m = 128 비트 폭이며,4개의 중간 저장 레지스터(4,28)가 제공되는 집적 회로.
- 제 1 항 내지 제 4 항 중 어느 한 항에 있어서,상기 플래쉬 메모리(1)의 액세스된 어드레스들을 저장하는 어드레스 태그 레지스터(address tag register)로 기여하는, 특히 추가적인 레지스터(5,25)인 제 2 수단과,상기 마이크로프로세서(3) 또는 상기 마이크로프로세서의 데이터 버스(8)에 의해서 요청된 현재 어드레스들을 이전에 액세스되어 상기 플래쉬 메모리(1)내에 저장된 어드레스들과 비교하는, 특히 비교기(6)인 제 3 수단을 더 포함하되,최근에 이용된 액세스들로부터의 데이터가 상기 마이크로프로세서(3)를 위한 캐쉬로 기여하는 상기 중간 저장 레지스터들(4,28)로부터 공급될 수 있는 집적 회로.
- 제 1 항 내지 제 5 항 중 어느 한 항에 있어서,상기 중간 저장 레지스터들(4,28)내의 데이터를 상기 마이크로프로세서 버스(8)로 멀티플렉싱(multiplexing)하는 멀티플렉서(7,27)를 더 포함하는 집적 회로.
- 제 1 항 내지 제 6 항 중 어느 한 항에 있어서,적어도 몇몇 IC 구성 요소, 특히 상기 중간 저장 레지스터들(4,28)의 로딩(loading) 및 언로딩(unloading)을 담당하는 구성 요소들의 기능을 제어하는 캐쉬 제어 수단(29)을 더 포함하는 집적 회로.
- 제 4 항, 제 6 항 및 제 7 항 중 어느 한 항에 있어서,상기 멀티플렉서(7,27)는 4×1 멀티플렉서(a four-to-one multiplexer)이며, 128 비트의 캐쉬 라인을 상기 마이크로프로세서(3)에 제공하는 집적 회로.
- 제 7 항 또는 제 8 항에 있어서,상기 캐쉬 제어 수단(29)은 상기 캐쉬 제어 수단이 데이터가 이용가능하게되는 것을 기다릴 때마다 대기 상태를 상기 마이크로프로세서 싸이클에 도입하도록 되어 있는 집적 회로.
- 제 1 항 내지 제 9 항 중 어느 한 항에 있어서,상기 캐쉬 제어 수단(29)은 5개의 상태, 특히 IDLE 상태(31), READ 상태, FBREQ(Flash Bus Request) 상태(33), HOLD 상태(34) 및 MISS 상태(35)를 가지는 상태 머신(a state machine)인 집적 회로.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00113609 | 2000-06-27 | ||
EP00113609.2 | 2000-06-27 | ||
PCT/EP2001/007009 WO2002001375A1 (en) | 2000-06-27 | 2001-06-20 | Integrated circuit with flash |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030009290A true KR20030009290A (ko) | 2003-01-29 |
KR100814247B1 KR100814247B1 (ko) | 2008-03-17 |
Family
ID=8169085
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020027002472A KR100814247B1 (ko) | 2000-06-27 | 2001-06-20 | 집적 회로 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6735661B2 (ko) |
EP (1) | EP1297434B1 (ko) |
JP (2) | JP5076133B2 (ko) |
KR (1) | KR100814247B1 (ko) |
AT (1) | ATE293810T1 (ko) |
DE (1) | DE60110227T2 (ko) |
WO (1) | WO2002001375A1 (ko) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
ATE293810T1 (de) * | 2000-06-27 | 2005-05-15 | Koninkl Philips Electronics Nv | Integrierte schaltung mit flash |
US7004917B2 (en) | 2001-03-29 | 2006-02-28 | Royce Medical Company | Hardenable orthopaedic support (free edge) |
WO2003094036A1 (en) * | 2002-04-30 | 2003-11-13 | Koninklijke Philips Electronics N.V. | Method for fetching data from a non-volatile memory in an integrated circuit and corresponding integrated circuit |
EP1499961A2 (en) * | 2002-04-30 | 2005-01-26 | Koninklijke Philips Electronics N.V. | Apparatus and method for fetching data from memory |
JP4031996B2 (ja) * | 2003-01-30 | 2008-01-09 | 富士フイルム株式会社 | メモリ装置を備えたディジタル・スチル・カメラ |
ITTO20030165A1 (it) * | 2003-03-06 | 2004-09-07 | Space Cannon Vh S P A | Proiettore di luce a led |
ITRM20030354A1 (it) | 2003-07-17 | 2005-01-18 | Micron Technology Inc | Unita' di controllo per dispositivo di memoria. |
ITMI20031893A1 (it) * | 2003-10-03 | 2005-04-04 | St Microelectronics Srl | Dispositivo integrato di memoria con comandi di lettura e scrittura multipli. |
US7173863B2 (en) | 2004-03-08 | 2007-02-06 | Sandisk Corporation | Flash controller cache architecture |
EP1711898B1 (en) * | 2004-02-05 | 2009-06-03 | Research In Motion Limited | System and method for detecting the width of a data bus |
KR100666169B1 (ko) * | 2004-12-17 | 2007-01-09 | 삼성전자주식회사 | 플래쉬 메모리 데이터 저장장치 |
US7882299B2 (en) | 2004-12-21 | 2011-02-01 | Sandisk Corporation | System and method for use of on-chip non-volatile memory write cache |
US20060218332A1 (en) * | 2005-03-25 | 2006-09-28 | Via Technologies, Inc. | Interface circuit, system, and method for interfacing between buses of different widths |
JP2008024411A (ja) * | 2006-07-20 | 2008-02-07 | Toshiba Elevator Co Ltd | エレベータ制御装置 |
US9195602B2 (en) | 2007-03-30 | 2015-11-24 | Rambus Inc. | System including hierarchical memory modules having different types of integrated circuit memory devices |
US8495020B1 (en) * | 2007-06-27 | 2013-07-23 | ENORCOM Corporation | Mobile information system |
US8086769B2 (en) * | 2008-01-17 | 2011-12-27 | International Business Machines Corporation | Method for detecting circular buffer overrun |
US8415978B2 (en) * | 2008-12-29 | 2013-04-09 | Stmicroelectronics S.R.L. | State machine for generating a pulse width modulation (PWM) waveform |
US7895381B2 (en) * | 2009-02-16 | 2011-02-22 | Himax Media Solutions, Inc. | Data accessing system |
US8707104B1 (en) | 2011-09-06 | 2014-04-22 | Western Digital Technologies, Inc. | Systems and methods for error injection in data storage systems |
US9195530B1 (en) | 2011-09-06 | 2015-11-24 | Western Digital Technologies, Inc. | Systems and methods for improved data management in data storage systems |
US8713357B1 (en) | 2011-09-06 | 2014-04-29 | Western Digital Technologies, Inc. | Systems and methods for detailed error reporting in data storage systems |
US8700834B2 (en) | 2011-09-06 | 2014-04-15 | Western Digital Technologies, Inc. | Systems and methods for an enhanced controller architecture in data storage systems |
US9053008B1 (en) | 2012-03-26 | 2015-06-09 | Western Digital Technologies, Inc. | Systems and methods for providing inline parameter service in data storage devices |
US9582204B2 (en) * | 2014-01-07 | 2017-02-28 | Apple Inc. | Speculative prefetching of data stored in flash memory |
US10031869B1 (en) | 2014-03-28 | 2018-07-24 | Adesto Technologies Corporation | Cached memory structure and operation |
US9910787B2 (en) * | 2014-06-05 | 2018-03-06 | Micron Technology, Inc. | Virtual address table |
KR20180031412A (ko) * | 2016-09-20 | 2018-03-28 | 삼성전자주식회사 | 메모리 컨트롤러의 동작 방법과, 이를 포함하는 장치들의 동작 방법들 |
US10489056B2 (en) * | 2017-11-09 | 2019-11-26 | Nvidia Corporation | Queue manager for streaming multiprocessor systems |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4953073A (en) * | 1986-02-06 | 1990-08-28 | Mips Computer Systems, Inc. | Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories |
JPH02272654A (ja) * | 1989-04-13 | 1990-11-07 | Nec Corp | キャッシュメモリ装置 |
US5732241A (en) * | 1990-06-27 | 1998-03-24 | Mos Electronics, Corp. | Random access cache memory controller and system |
JPH06266596A (ja) * | 1993-03-11 | 1994-09-22 | Hitachi Ltd | フラッシュメモリファイル記憶装置および情報処理装置 |
JPH08503328A (ja) | 1993-07-29 | 1996-04-09 | アトメル・コーポレイション | マイクロコントローラのための遠隔再プログラム可能プログラムメモリ |
US6026027A (en) * | 1994-01-31 | 2000-02-15 | Norand Corporation | Flash memory system having memory cache |
US5726937A (en) * | 1994-01-31 | 1998-03-10 | Norand Corporation | Flash memory system having memory cache |
JPH07325898A (ja) * | 1994-06-02 | 1995-12-12 | Hitachi Ltd | 記憶装置 |
US5696929A (en) * | 1995-10-03 | 1997-12-09 | Intel Corporation | Flash EEPROM main memory in a computer system |
JPH09231130A (ja) * | 1996-02-26 | 1997-09-05 | Mitsubishi Electric Corp | マイクロコンピュータ |
US5937174A (en) * | 1996-06-28 | 1999-08-10 | Lsi Logic Corporation | Scalable hierarchial memory structure for high data bandwidth raid applications |
US5860097A (en) * | 1996-09-23 | 1999-01-12 | Hewlett-Packard Company | Associative cache memory with improved hit time |
US5768287A (en) * | 1996-10-24 | 1998-06-16 | Micron Quantum Devices, Inc. | Apparatus and method for programming multistate memory device |
WO1998018078A1 (fr) * | 1996-10-24 | 1998-04-30 | Mitsubishi Denki Kabushiki Kaisha | Micro-ordinateur dont la memoire et le processeur se trouvent sur une meme puce |
US5903916A (en) * | 1996-12-16 | 1999-05-11 | Intel Corporation | Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation |
US5937423A (en) * | 1996-12-26 | 1999-08-10 | Intel Corporation | Register interface for flash EEPROM memory arrays |
US5802602A (en) * | 1997-01-17 | 1998-09-01 | Intel Corporation | Method and apparatus for performing reads of related data from a set-associative cache memory |
US5822251A (en) * | 1997-08-25 | 1998-10-13 | Bit Microsystems, Inc. | Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers |
US6088777A (en) * | 1997-11-12 | 2000-07-11 | Ericsson Messaging Systems, Inc. | Memory system and method for dynamically allocating a memory divided into plural classes with different block sizes to store variable length messages |
US6308241B1 (en) * | 1997-12-22 | 2001-10-23 | U.S. Philips Corporation | On-chip cache file register for minimizing CPU idle cycles during cache refills |
JP3732637B2 (ja) * | 1997-12-26 | 2006-01-05 | 株式会社ルネサステクノロジ | 記憶装置、記憶装置のアクセス方法及び半導体装置 |
US6425065B2 (en) * | 1997-12-31 | 2002-07-23 | Intel Corporation | Tag RAM with selection module for a variable width address field |
US6041400A (en) | 1998-10-26 | 2000-03-21 | Sony Corporation | Distributed extensible processing architecture for digital signal processing applications |
WO2000025208A1 (en) | 1998-10-28 | 2000-05-04 | Zf Linux Devices, Inc. | Processor system with fail safe bios configuration |
US6282643B1 (en) * | 1998-11-20 | 2001-08-28 | International Business Machines Corporation | Computer system having flash memory BIOS which can be accessed remotely while protected mode operating system is running |
JP2000276402A (ja) * | 1999-03-24 | 2000-10-06 | Kokusai Electric Co Ltd | フラッシュメモリ駆動方法及びフラッシュメモリ装置 |
US6321315B1 (en) * | 1999-09-30 | 2001-11-20 | Micron Technology, Inc. | Method and apparatus to reduce memory read latency |
US6434674B1 (en) * | 2000-04-04 | 2002-08-13 | Advanced Digital Information Corporation | Multiport memory architecture with direct data flow |
ATE293810T1 (de) * | 2000-06-27 | 2005-05-15 | Koninkl Philips Electronics Nv | Integrierte schaltung mit flash |
KR100805603B1 (ko) * | 2000-06-27 | 2008-02-20 | 엔엑스피 비 브이 | 집적 회로 |
US6836816B2 (en) * | 2001-03-28 | 2004-12-28 | Intel Corporation | Flash memory low-latency cache |
-
2001
- 2001-06-20 AT AT01960346T patent/ATE293810T1/de not_active IP Right Cessation
- 2001-06-20 WO PCT/EP2001/007009 patent/WO2002001375A1/en active IP Right Grant
- 2001-06-20 EP EP01960346A patent/EP1297434B1/en not_active Expired - Lifetime
- 2001-06-20 DE DE60110227T patent/DE60110227T2/de not_active Expired - Lifetime
- 2001-06-20 KR KR1020027002472A patent/KR100814247B1/ko active IP Right Grant
- 2001-06-20 JP JP2002506443A patent/JP5076133B2/ja not_active Expired - Lifetime
- 2001-06-26 US US09/891,449 patent/US6735661B2/en not_active Expired - Lifetime
-
2012
- 2012-06-22 JP JP2012140982A patent/JP2012198935A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
ATE293810T1 (de) | 2005-05-15 |
JP2012198935A (ja) | 2012-10-18 |
JP2004502240A (ja) | 2004-01-22 |
US20020013874A1 (en) | 2002-01-31 |
DE60110227D1 (de) | 2005-05-25 |
EP1297434A1 (en) | 2003-04-02 |
DE60110227T2 (de) | 2006-02-09 |
KR100814247B1 (ko) | 2008-03-17 |
WO2002001375A1 (en) | 2002-01-03 |
JP5076133B2 (ja) | 2012-11-21 |
US6735661B2 (en) | 2004-05-11 |
EP1297434B1 (en) | 2005-04-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100814247B1 (ko) | 집적 회로 | |
US9626303B2 (en) | Data processing apparatus and address space protection method | |
US9158725B2 (en) | Flexible control mechanism for store gathering in a write buffer | |
US5752272A (en) | Memory access control device with prefetch and read out block length control functions | |
US5809524A (en) | Method and apparatus for cache memory replacement line identification | |
PL176554B1 (pl) | Sposób przesyłania informacji między jednostką przetwarzającą systemu komputerowego, zewnętrzną pamięcią podręczną i pamięcią główną oraz system komputerowy | |
US9009411B2 (en) | Flexible control mechanism for store gathering in a write buffer | |
JP4434534B2 (ja) | プロセッサ・システム | |
JP2009512933A (ja) | アクセス性の高いストア帯域幅を備えたキャッシュ | |
US6564272B1 (en) | Non-coherent cache buffer for read accesses to system memory | |
EP0797148B1 (en) | Multi-mode cache structure | |
US6871246B2 (en) | Prefetch control in a data processing system | |
US20070299991A1 (en) | DMA module and operating system therefor | |
US9003158B2 (en) | Flexible control mechanism for store gathering in a write buffer | |
EP1367493A1 (en) | Prefetch buffer | |
JPH11232100A (ja) | 単一サイクル内に間接アドレシングモードアドレスを出力するデータポインタおよびその方法 | |
US5749092A (en) | Method and apparatus for using a direct memory access unit and a data cache unit in a microprocessor | |
JP3964049B2 (ja) | マイクロプロセッサ | |
JPH10293684A (ja) | コンピュータシステムおよびその立ち上げ制御方法 | |
JP2689920B2 (ja) | 演算処理システムに用いられるプリフェッチバッファ装置 | |
KR200190099Y1 (ko) | 메모리 겸용 캐시 | |
JP2009259087A (ja) | メモリ制御回路 | |
KR19990040197A (ko) | 메모리 겸용 캐시 | |
JPH11143773A (ja) | データ処理装置及びデータ処理システム | |
JPH0261737A (ja) | 記憶装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
N231 | Notification of change of applicant | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
G170 | Re-publication after modification of scope of protection [patent] | ||
FPAY | Annual fee payment |
Payment date: 20130227 Year of fee payment: 6 |
|
FPAY | Annual fee payment |
Payment date: 20140221 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20150226 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20160224 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20170307 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20180228 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20190227 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20200303 Year of fee payment: 13 |