JP4620437B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4620437B2 JP4620437B2 JP2004349702A JP2004349702A JP4620437B2 JP 4620437 B2 JP4620437 B2 JP 4620437B2 JP 2004349702 A JP2004349702 A JP 2004349702A JP 2004349702 A JP2004349702 A JP 2004349702A JP 4620437 B2 JP4620437 B2 JP 4620437B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- buried layer
- voltage
- impurity region
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 175
- 239000012535 impurity Substances 0.000 claims description 218
- 239000000758 substrate Substances 0.000 claims description 91
- 230000005684 electric field Effects 0.000 description 94
- 230000015556 catabolic process Effects 0.000 description 62
- 230000003071 parasitic effect Effects 0.000 description 58
- 238000009826 distribution Methods 0.000 description 52
- 238000010586 diagram Methods 0.000 description 30
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000002955 isolation Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000008929 regeneration Effects 0.000 description 4
- 238000011069 regeneration method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0886—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
Description
図1は、本発明の実施の形態1に係る高圧側駆動部101の構造を示す断面図であり、図57に示したラインB−Bに沿った位置に関する断面図に相当する。図1を参照して、p-基板200の上面内には、p+分離201、n-型不純物領域110、及びn型不純物領域117,121が形成されている。n型不純物領域121の上面内には、pウェル131が形成されている。p+分離201はp-基板200に達しており、p-基板200の電位は、回路上最も低い電位(GND電位又はCOM電位)となっている。また、高耐圧MOS11のn+型ソース領域112の下部にpウェル111が形成されており、pウェル111は、ゲート絶縁膜115aを介してゲート電極116aの下部に達し、高耐圧MOS11のチャネル領域を形成している。さらに、pウェル111の上面内には、ソース電極114に接するようにp+型不純物領域113及びn+型ソース領域112が形成されている。また、n型不純物領域117の上面内には、高耐圧MOS11のドレイン電極119に接するようにn+型ドレイン領域118が形成されている。
図8は、図1に対応させて、本発明の実施の形態2に係る高圧側駆動部101の構造を示す断面図である。図1に示したn+埋め込み層20の代わりに、n+埋め込み層20よりも不純物濃度が高いn+型不純物領域(以下「n+埋め込み層」と称す)22が形成されている。一例として、n+埋め込み層22の不純物濃度のピーク値は、1018cm-3のオーダーである。n+埋め込み層22は、n+埋め込み層20と同様に、n型不純物領域121の底面に接してp-基板200内に形成されている。
図13は、図1に対応させて、本発明の実施の形態3に係る高圧側駆動部101の構造を示す断面図である。図1に示したn+埋め込み層20の代わりに、n型不純物領域121よりも不純物濃度が高いn+型不純物領域(以下「n+埋め込み層」と称す)23と、n+埋め込み層23よりも不純物濃度が低いn型不純物領域(以下「n埋め込み層」と称す)24とが形成されている。一例として、n+埋め込み層23の不純物濃度のピーク値は1018cm-3のオーダーであり、n埋め込み層24の不純物濃度のピーク値は1015cm-3のオーダーである。n+埋め込み層23は、n+埋め込み層20と同様に、n型不純物領域121の底面に接してp-基板200内に形成されている。また、n埋め込み層24は、n型不純物領域121の底面に接しつつn+埋め込み層23の周囲を覆って、p-基板200内に形成されている。
図16は、従来の半導体装置に関する図67に対応して、本発明の実施の形態4に係る半導体装置に関し、図59に示した構造のうち高耐圧ダイオード14が形成されている領域の構造を抜き出して詳細に示した断面図である。図16では、説明の都合上、アノードとカソードとの形成箇所の関係が、図59に示した関係とは逆になっている。
図24は、図16に対応して、本発明の実施の形態5に係る半導体装置の構造を示す断面図である。図16に示した構造を基礎として、n埋め込み層26よりも不純物濃度が高いn+型不純物領域(以下「n+埋め込み層」と称す)27が、n埋め込み層26内に形成されている。一例として、n+埋め込み層27の不純物濃度のピーク値は、1018cm-3のオーダーである。n+埋め込み層27の幅L3はn埋め込み層26の幅L1よりも小さく、その結果、n+埋め込み層27は、n埋め込み層26の側面(図24における右側面)よりもアノード電極145側に突出しないように形成されている。
さらに、本実施の形態5に係る半導体装置では、n埋め込み層26内にn+埋め込み層27が形成されている。そのため、n+埋め込み層27が形成されていない上記実施の形態4に係る半導体装置と比較すると、p-基板200と、n型不純物領域121、n埋め込み層26、及びn+埋め込み層27と、pウェル131とから成るpnp構造に起因する寄生pnpバイポーラトランジスタのベース抵抗が低減される。従って、回生期間に高圧側浮遊オフセット電圧VSの負変動が生じた場合であっても、寄生pnpバイポーラトランジスタの動作が抑制される。その結果、p-基板200と、n型不純物領域121、n埋め込み層26、及びn+埋め込み層27と、pウェル131と、n+型ソース領域133とから成るpnpn構造に起因する寄生サイリスタの動作開始電圧の絶対値を、上記実施の形態4に係る半導体装置よりも高めることができ、ひいてはCMOS12のラッチアップ破壊耐量を高めることもできる。
図33は、従来の半導体装置に関する図70に対応して、本発明の実施の形態6に係る半導体装置に関し、図58に示した構造のうち高耐圧MOS11が形成されている領域の構造を抜き出して示した断面図である。図33では、説明の都合上、ドレイン領域118とソース領域112との形成箇所の関係が、図58に示した関係とは逆になっている。
図38は、図33に対応して、本発明の実施の形態7に係る半導体装置の構造を示す断面図である。図33に示した構造を基礎として、n埋め込み層29よりも不純物濃度が高いn+型不純物領域(以下「n+埋め込み層」と称す)30が、n埋め込み層29内に形成されている。一例として、n+埋め込み層30の不純物濃度のピーク値は、1018cm-3のオーダーである。n+埋め込み層30の幅L6は、n埋め込み層29の幅L4及びn型不純物領域121の幅L7よりも小さい。つまり、n+埋め込み層30は、n埋め込み層29の側面(図38における右側面)及びn型不純物領域121の側面(図38における右側面)よりもn型不純物領域117側に突出しないように形成されている。
上記実施の形態1〜3に係る発明は、パワーデバイス駆動装置の低圧側駆動部に適用することも可能である。
図44には、図2の(A)に対応させて、本発明の実施の形態9に係る半導体装置におけるCMOS部の簡易な構造を示す断面図である。本実施の形態9に係る半導体装置では、上記実施の形態1に係る半導体装置におけるn+埋め込み層20の代わりに、n+埋め込み層20よりも高濃度のn+型不純物領域(以下「n+埋め込み層」と称す)31が形成されている。一例として、n+埋め込み層31の不純物濃度のピーク値は、1018cm-3のオーダーである。
Claims (1)
- 第1電極、第2電極、及び制御電極を有するスイッチングデバイスを駆動するための半導体装置であって、
前記第1電極に接続された第1の端子と、
容量性素子を介して前記第1電極に接続された第2の端子と、
第1導電型の半導体基板と、
前記半導体基板の主面内に形成された、第2導電型の第1の不純物領域と、
前記第1の不純物領域の主面内に形成された、前記第1導電型の第2の不純物領域と、
前記第2の不純物領域の主面内に形成され、前記第1の端子に接続された、前記第2導電型のソース・ドレイン領域を有する、第1のトランジスタと、
前記第1の不純物領域の前記主面内に形成され、前記第2の端子に接続された、前記第1導電型のソース・ドレイン領域を有する、第2のトランジスタと、
前記第1の不純物領域の底面に接して前記半導体基板内に形成された、前記第2導電型の第3の不純物領域と
を備え、
前記第3の不純物領域は、
前記第1の不純物領域の前記底面に接して前記半導体基板内に形成され、前記第1の不純物領域が有する第1の不純物濃度よりも高い第2の不純物濃度を有する、前記第2導電型の高濃度不純物領域と、
前記第1の不純物領域の前記底面に接し、前記高濃度不純物領域の周囲を覆って前記半導体基板内に形成され、前記第2の不純物濃度よりも低い第3の不純物濃度を有する、前記第2導電型の低濃度不純物領域と
を有する、半導体装置。
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004349702A JP4620437B2 (ja) | 2004-12-02 | 2004-12-02 | 半導体装置 |
TW094119041A TWI277197B (en) | 2004-12-02 | 2005-06-09 | Semiconductor device |
US11/194,532 US7812402B2 (en) | 2004-12-02 | 2005-08-02 | Semiconductor device |
DE102005063426A DE102005063426B4 (de) | 2004-12-02 | 2005-08-03 | Halbleitervorrichtung |
DE102005063427A DE102005063427B4 (de) | 2004-12-02 | 2005-08-03 | Halbleitervorrichtung |
DE102005036543A DE102005036543B4 (de) | 2004-12-02 | 2005-08-03 | Halbleitervorrichtung |
CNB2005101188964A CN100426506C (zh) | 2004-12-02 | 2005-11-02 | 半导体装置 |
KR1020050104099A KR100756304B1 (ko) | 2004-12-02 | 2005-11-02 | 반도체장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004349702A JP4620437B2 (ja) | 2004-12-02 | 2004-12-02 | 半導体装置 |
Related Child Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010200412A Division JP5138748B2 (ja) | 2010-09-08 | 2010-09-08 | 半導体装置 |
JP2010200414A Division JP5191515B2 (ja) | 2010-09-08 | 2010-09-08 | 半導体装置 |
JP2010200413A Division JP5191514B2 (ja) | 2010-09-08 | 2010-09-08 | 半導体装置 |
JP2010200415A Division JP5191516B2 (ja) | 2010-09-08 | 2010-09-08 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006165026A JP2006165026A (ja) | 2006-06-22 |
JP4620437B2 true JP4620437B2 (ja) | 2011-01-26 |
Family
ID=36441832
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004349702A Active JP4620437B2 (ja) | 2004-12-02 | 2004-12-02 | 半導体装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7812402B2 (ja) |
JP (1) | JP4620437B2 (ja) |
KR (1) | KR100756304B1 (ja) |
CN (1) | CN100426506C (ja) |
DE (3) | DE102005063427B4 (ja) |
TW (1) | TWI277197B (ja) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7385246B2 (en) * | 2005-07-22 | 2008-06-10 | Intersil Americas Inc. | Depletable cathode low charge storage diode |
JP2007242671A (ja) * | 2006-03-06 | 2007-09-20 | Matsushita Electric Ind Co Ltd | 半導体集積回路 |
JP5055813B2 (ja) * | 2006-04-10 | 2012-10-24 | 富士電機株式会社 | Soi横型半導体装置 |
JP4632068B2 (ja) * | 2008-05-30 | 2011-02-16 | 三菱電機株式会社 | 半導体装置 |
JP5487851B2 (ja) * | 2008-09-30 | 2014-05-14 | サンケン電気株式会社 | 半導体装置 |
JP5045733B2 (ja) * | 2008-12-24 | 2012-10-10 | 株式会社デンソー | 半導体装置 |
JP5503897B2 (ja) | 2009-05-08 | 2014-05-28 | 三菱電機株式会社 | 半導体装置 |
CN103258851A (zh) * | 2012-02-15 | 2013-08-21 | 立锜科技股份有限公司 | 隔离元件及其制造方法 |
US9330922B2 (en) | 2012-03-07 | 2016-05-03 | Silicon Storage Technology, Inc. | Self-aligned stack gate structure for use in a non-volatile memory array and a method of forming such structure |
KR101941295B1 (ko) * | 2013-08-09 | 2019-01-23 | 매그나칩 반도체 유한회사 | 반도체 소자 |
JP6228428B2 (ja) | 2013-10-30 | 2017-11-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10784372B2 (en) * | 2015-04-03 | 2020-09-22 | Magnachip Semiconductor, Ltd. | Semiconductor device with high voltage field effect transistor and junction field effect transistor |
KR101975630B1 (ko) * | 2015-04-03 | 2019-08-29 | 매그나칩 반도체 유한회사 | 접합 트랜지스터와 고전압 트랜지스터 구조를 포함한 반도체 소자 및 그 제조 방법 |
US10205024B2 (en) * | 2016-02-05 | 2019-02-12 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure having field plate and associated fabricating method |
KR102227666B1 (ko) * | 2017-05-31 | 2021-03-12 | 주식회사 키 파운드리 | 고전압 반도체 소자 |
JP7043825B2 (ja) | 2017-12-15 | 2022-03-30 | 富士電機株式会社 | 半導体集積回路 |
JP7300968B2 (ja) * | 2019-11-14 | 2023-06-30 | 三菱電機株式会社 | 半導体装置 |
CN111312707B (zh) * | 2020-02-27 | 2022-11-04 | 电子科技大学 | 一种低比导通电阻的功率半导体器件 |
CN112201685B (zh) * | 2020-09-08 | 2022-02-11 | 浙江大学 | 一种超级结器件及电介质组合终端 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11214530A (ja) * | 1998-01-27 | 1999-08-06 | Matsushita Electric Works Ltd | 高耐圧半導体装置 |
JPH11214531A (ja) * | 1998-01-27 | 1999-08-06 | Matsushita Electric Works Ltd | 高耐圧半導体装置及びその製造方法 |
JP2002324848A (ja) * | 2001-02-20 | 2002-11-08 | Mitsubishi Electric Corp | 半導体装置 |
JP2003068872A (ja) * | 2001-06-04 | 2003-03-07 | Matsushita Electric Ind Co Ltd | 高耐圧半導体装置 |
JP2004047937A (ja) * | 2002-05-24 | 2004-02-12 | Mitsubishi Electric Corp | 半導体装置 |
JP2004241613A (ja) * | 2003-02-06 | 2004-08-26 | Ricoh Co Ltd | 半導体装置 |
JP2004296831A (ja) * | 2003-03-27 | 2004-10-21 | Mitsubishi Electric Corp | 半導体装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1131801A (en) * | 1978-01-18 | 1982-09-14 | Johannes A. Appels | Semiconductor device |
JPS6473661A (en) * | 1987-09-14 | 1989-03-17 | Nec Corp | Complementary semiconductor device |
JPH05152523A (ja) | 1992-05-18 | 1993-06-18 | Seiko Epson Corp | 相補型mis半導体集積回路装置 |
JP3547884B2 (ja) * | 1995-12-30 | 2004-07-28 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JP3917211B2 (ja) * | 1996-04-15 | 2007-05-23 | 三菱電機株式会社 | 半導体装置 |
JPH1197646A (ja) * | 1997-09-22 | 1999-04-09 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US7078298B2 (en) | 2003-05-20 | 2006-07-18 | Sharp Laboratories Of America, Inc. | Silicon-on-nothing fabrication process |
JP4326835B2 (ja) * | 2003-05-20 | 2009-09-09 | 三菱電機株式会社 | 半導体装置、半導体装置の製造方法及び半導体装置の製造プロセス評価方法 |
-
2004
- 2004-12-02 JP JP2004349702A patent/JP4620437B2/ja active Active
-
2005
- 2005-06-09 TW TW094119041A patent/TWI277197B/zh not_active IP Right Cessation
- 2005-08-02 US US11/194,532 patent/US7812402B2/en active Active
- 2005-08-03 DE DE102005063427A patent/DE102005063427B4/de active Active
- 2005-08-03 DE DE102005063426A patent/DE102005063426B4/de active Active
- 2005-08-03 DE DE102005036543A patent/DE102005036543B4/de active Active
- 2005-11-02 KR KR1020050104099A patent/KR100756304B1/ko active IP Right Grant
- 2005-11-02 CN CNB2005101188964A patent/CN100426506C/zh active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11214530A (ja) * | 1998-01-27 | 1999-08-06 | Matsushita Electric Works Ltd | 高耐圧半導体装置 |
JPH11214531A (ja) * | 1998-01-27 | 1999-08-06 | Matsushita Electric Works Ltd | 高耐圧半導体装置及びその製造方法 |
JP2002324848A (ja) * | 2001-02-20 | 2002-11-08 | Mitsubishi Electric Corp | 半導体装置 |
JP2003068872A (ja) * | 2001-06-04 | 2003-03-07 | Matsushita Electric Ind Co Ltd | 高耐圧半導体装置 |
JP2004047937A (ja) * | 2002-05-24 | 2004-02-12 | Mitsubishi Electric Corp | 半導体装置 |
JP2004241613A (ja) * | 2003-02-06 | 2004-08-26 | Ricoh Co Ltd | 半導体装置 |
JP2004296831A (ja) * | 2003-03-27 | 2004-10-21 | Mitsubishi Electric Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
DE102005063427B4 (de) | 2012-05-16 |
KR20060061884A (ko) | 2006-06-08 |
JP2006165026A (ja) | 2006-06-22 |
DE102005036543B4 (de) | 2011-04-21 |
DE102005063426B4 (de) | 2012-01-19 |
US7812402B2 (en) | 2010-10-12 |
TW200620629A (en) | 2006-06-16 |
DE102005036543A1 (de) | 2006-06-08 |
CN1783495A (zh) | 2006-06-07 |
US20060118860A1 (en) | 2006-06-08 |
TWI277197B (en) | 2007-03-21 |
KR100756304B1 (ko) | 2007-09-06 |
CN100426506C (zh) | 2008-10-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100756304B1 (ko) | 반도체장치 | |
KR100789308B1 (ko) | 반도체장치 | |
US9412732B2 (en) | Semiconductor device | |
CN107534017B (zh) | 半导体装置 | |
US8686531B2 (en) | Structure and method for forming a guard ring to protect a control device in a power semiconductor IC | |
KR100749231B1 (ko) | 반도체 장치 | |
JP6226101B2 (ja) | 半導体集積回路 | |
JP5072043B2 (ja) | 半導体装置 | |
JP6677672B2 (ja) | 半導体装置 | |
KR100842340B1 (ko) | 반도체 집적회로 장치 | |
JPWO2016132418A1 (ja) | 半導体集積回路 | |
JP4531276B2 (ja) | 半導体装置 | |
JP5191514B2 (ja) | 半導体装置 | |
JP5138748B2 (ja) | 半導体装置 | |
JP4945948B2 (ja) | 半導体装置 | |
JP5191516B2 (ja) | 半導体装置 | |
JP5191515B2 (ja) | 半導体装置 | |
JP4525629B2 (ja) | レベルシフタ | |
JP5256750B2 (ja) | 半導体装置 | |
JP2004273793A (ja) | 半導体装置 | |
JP2010010264A (ja) | 半導体装置 | |
JP2009231851A (ja) | 半導体装置 | |
JP2009266934A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20061211 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090730 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20091106 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100720 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100908 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101026 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20101028 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131105 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4620437 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |