JP5503897B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5503897B2 JP5503897B2 JP2009113590A JP2009113590A JP5503897B2 JP 5503897 B2 JP5503897 B2 JP 5503897B2 JP 2009113590 A JP2009113590 A JP 2009113590A JP 2009113590 A JP2009113590 A JP 2009113590A JP 5503897 B2 JP5503897 B2 JP 5503897B2
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- H03—ELECTRONIC CIRCUITRY
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Description
図1は、この発明に従うパワーデバイス駆動用の半導体装置の外部接続態様を示す図である。図1において、高耐圧制御回路(半導体装置)HVICが、ローサイドパワートランジスタQ1およびハイサイドパワートランジスタQ2のオン/オフを設定する。パワートランジスタQ1およびQ2は、一例として、IGBT(絶縁ゲート型バイポーラトランジスタ)で構成され、ドレインおよびソースの間に、それぞれ、フリーホイールダイオードD1およびD2が逆並列に接続される。
図8は、この発明の実施の形態2に従う高耐圧制御回路HVICの平面レイアウトを概略的に示す図である。図8に示す高耐圧制御回路HVICの構成において、VSクランプ用の高耐圧ダイオードが、高電位側ロジック回路12が形成される高耐圧電位島領域9内部に配置される高耐圧分離領域10を利用して形成される。すなわち、高耐圧分離領域10において、クランプ用の高耐圧ダイオード(D3)のアノード電極70が、高耐圧分離領域10の全周に沿って連続的に延在してトラック形状に形成される。高耐圧分離領域10内部に、カソード電極72がトラック形状に連続的に形成される。カソード電極72と高電位側ロジック回路領域76の間に、スリット領域74が設けられる。このスリット領域764により、高耐圧ダイオード(D3)を形成するN型半導体層と高電位側ロジック回路2を形成するN型半導体層とが分離される。
図10は、この発明の実施の形態3に従う高耐圧制御回路HVICの平面レイアウトを概略的に示す図である。この図10に示す高耐圧制御回路HVICにおいては、共通接地ノードCOMに結合される共通接地パッド6は、内部配線7Aを介して低電位側ロジック回路1に結合される。共通接地ノードCOMからの接地電圧GNDは、高耐圧制御回路HVICが形成されるP型半導体基板(29)に供給される。
図12は、この発明の実施の形態4に従う高耐圧ダイオードD3の断面構造を概略的に示す図である。この図12に示す高耐圧ダイオードの構造は、図9に示す高電圧ダイオードの構成と、以下の点でその構造が異なる。すなわち、P型半導体基板29の裏面に、裏面金属電極100が形成される。この図12に示す高耐圧ダイオードの他の構成は、図9に示す高耐圧ダイオードの断面構造と同じであり、対応する部分には同一参照番号を付し、その詳細説明は省略する。また、実施の形態4における高耐圧制御回路HVICの平面レイアウトは、図8に示す平面レイアウトと同じとなる。図12に示す高耐圧ダイオードの構造は図9に示す高耐圧ダイオードの構造と同じであり、対応する部分には同一参照番号を付し、その詳細説明は省略する。
図13は、この発明の実施の形態5に従う高耐圧制御回路HVICの高耐圧ダイオード部分の断面構造を概略的に示す図である。図13に示す高耐圧ダイオードは、以下の点で、図12に示す高耐圧ダイオードとその構成が異なる。すなわち、P型半導体基板29の裏面に形成される裏面金属電極100に対してさらに、金属リードフレーム110が付着される。この金属リードフレーム110は、共通接地ノードCOMに接続される。図13に示す高耐圧ダイオードの他の構造は、図12に示す高耐圧ダイオードの構造と同じであり、対応する部分には同一参照番号を付し、その詳細説明は省略する。
図15は、この発明の実施の形態6に従う半導体装置の高耐圧ダイオード部分の断面構造を概略的に示す図である。図15に示す高耐圧ダイオードの構成自体は、図12に示す高耐圧ダイオードの断面構造と同じであり、対応する部分には同一参照番号を付し、その詳細説明は省略する。
図16は、この発明の実施の形態7に従う半導体装置の高耐圧ダイオードの断面構造を概略的に示す図である。この図16に示す高耐圧ダイオードの構造は、以下の点で、図15に示す高耐圧ダイオードの構造と異なる。すなわち、P型半導体基板29と裏面金属電極100の間に高濃度P型半導体層135が設けられる。この図16に示す高耐圧ダイオードの他の構成は、図15に示す高耐圧ダイオードの構成と同じであり、対応する部分には同一参照番号を付し、その詳細説明は省略する。
V=Em・WD/2 …(2)
式(2)に示すように、空乏層内における電界強度Eの積分値が、印加電圧Vとなり、ほぼ、図17に示す電界強度Eの直線LL1により囲まれる三角形の面積に等しくなる。
図19は、この発明の実施の形態8に従う半導体装置の高耐圧ダイオードの断面構造を概略的に示す図である。この図19に示す高耐圧ダイオードの平面レイアウトは、図10に示す半導体装置の平面レイアウトのそれと同じである。
図20は、この発明の実施の形態9に従う半導体装置の高耐圧ダイオードの断面構造を概略的に示す図である。図20に示す高耐圧ダイオードの構造は、以下の点で、図9に示す高耐圧ダイオードとその構造が異なる。すなわち、カソード電極配線82に接続される高濃度N型不純物領域81下部に、N型半導体層30bを横切ってP型半導体基板29に到達するように高濃度N型埋込不純物領域150が設けられる。この図20に示す高耐圧ダイオードの他の構造は、図9に示す高耐圧ダイオードの構造と同じであり、対応する部分には同一参照番号を付し、その詳細説明は省略する。
図21は、この発明の実施の形態9の変更例の高耐圧ダイオードの断面構造を概略的に示す図である。この図21に示す高耐圧ダイオードは、以下の点で、図11に示す高耐圧ダイオードとその構造が異なる。すなわち、VSパッド11の領域において高濃度N型不純物領域92下部に、N型半導体層90を越えてP型半導体基板29内部にまで延在するように高濃度N型埋込不純物領域150Bが設けられる。この図21に示す高耐圧ダイオードの他の構造は、図11に示す高耐圧ダイオードとその構造が同じであり、対応する部分には同一参照番号を付し、その詳細説明は省略する。
図22は、この発明の実施の形態10に従う半導体装置の高耐圧ダイオードの断面構造を概略的に示す図である。この図22に示す高耐圧ダイオードの構造は、以下の点で、図11に示す高耐圧ダイオードの構造と異なる。すなわち、高耐圧ダイオードD3のカソード電極を形成する電極配線93Aは、スリット領域86を越えて外部のN型半導体層95上部にまで形成される。この図22に示す高耐圧ダイオードの他の構造は、図11に示す高耐圧ダイオードの構造と同じであり、対応する部分には同一参照番号を付し、その詳細説明は省略する。
Claims (13)
- 高電位側および低電位側パワーデバイスを駆動する半導体装置であって、
前記低電位側パワーデバイスを駆動する低電位側回路が配置される低電位領域と、
前記低電位領域と同一半導体基板領域上に形成され、高電圧が印加されて前記高電位側パワーデバイスを駆動する高電位側回路が配置される高電位領域、
前記高電位領域に配置され、前記高電位側および低電位側パワーデバイスの接続ノードに結合され、前記高電位側回路に対する仮想接地電位を供給する仮想接地電極パッド、
前記低電位側回路および高電位側回路に対し共通に接地電位を供給する共通接地電極パッド、および
前記半導体基板領域上に形成され、カソードが前記仮想接地電極パッドに電気的に接続され、アノードが前記共通接地電極パッドに電気的に接続される高耐圧ダイオードを備え、
前記半導体基板領域は、第1の導電型を有し、
前記高耐圧ダイオードは、前記高電位領域および前記低電位領域の間に配置され、
前記高耐圧ダイオードは、
前記半導体基板領域上に形成され、前記高耐圧ダイオードのカソードとなる第2導電型の第1の半導体領域と、
前記第1の半導体領域を囲むように形成されるとともに前記半導体基板領域に到達するように形成されて前記高耐圧ダイオードのアノードとなる第1導電型の第2の半導体領域とを備え、前記第2の半導体領域は、前記第1の半導体領域を前記低電位領域および前記高電位領域の前記半導体基板領域上に形成される第2導電型の半導体領域と電気的に分離する、半導体装置。 - 高電位側および低電位側パワーデバイスを駆動する半導体装置であって、
前記低電位側パワーデバイスを駆動する低電位側回路が配置される低電位領域と、
前記低電位領域と同一半導体基板領域上に形成され、高電圧が印加されて前記高電位側パワーデバイスを駆動する高電位側回路が配置される高電位領域、
前記高電位領域に配置され、前記高電位側および低電位側パワーデバイスの接続ノードに結合され、前記高電位側回路に対する仮想接地電位を供給する仮想接地電極パッド、
前記低電位側回路および高電位側回路に対し共通に接地電位を供給する共通接地電極パッド、および
前記半導体基板領域上に形成され、カソードが前記仮想接地電極パッドに電気的に接続され、アノードが前記共通接地電極パッドに電気的に接続される高耐圧ダイオードを備え、
前記半導体基板領域は、第1の導電型を有し、
前記高耐圧ダイオードは、
前記半導体基板領域上に前記高電位領域を囲むように形成されて前記高耐圧ダイオードのカソードとなる第2導電型の第1の半導体領域と、
前記第1の半導体領域を囲むように形成されるとともに前記半導体基板領域に到達するように形成されて前記高耐圧ダイオードのアノードとなる第1導電型の第2の半導体領域とを備え、
前記高電位領域は、前記第1の半導体領域と離れて前記半導体基板領域上に形成されて前記高電位側回路のハイ側電源電圧が印加される第1導電型の第3の半導体領域を含む、半導体装置。 - 高電位側および低電位側パワーデバイスを駆動する半導体装置であって、
前記低電位側パワーデバイスを駆動する低電位側回路が配置される低電位領域と、
前記低電位領域と同一半導体基板領域上に形成され、高電圧が印加されて前記高電位側パワーデバイスを駆動する高電位側回路が配置される高電位領域、
前記高電位領域に配置され、前記高電位側および低電位側パワーデバイスの接続ノードに結合され、前記高電位側回路に対する仮想接地電位を供給する仮想接地電極パッド、
前記低電位側回路および高電位側回路に対し共通に接地電位を供給する共通接地電極パッド、および
前記半導体基板領域上に形成され、カソードが前記仮想接地電極パッドに電気的に接続され、アノードが前記共通接地電極パッドに電気的に接続される高耐圧ダイオードを備え、
前記高耐圧ダイオードは、
前記仮想接地電極パッドを構成する電極に接して前記半導体基板領域上に形成され、前記仮想接地電極と電気的に接続され前記高耐圧ダイオードのカソードとなる第1導電型の第1の半導体領域を備え、前記半導体基板領域が第2導電型を有し前記高耐圧ダイオードのアノードとなる、半導体装置。 - 前記カソード電極は、前記仮想接地電極下部に前記第1の半導体領域表面に接触する形成される電極部分と前記第1の半導体領域上に絶縁膜を介して形成されるプレート部分とを有する導電膜を備える、請求項3記載の半導体装置。
- 前記アノードは、前記半導体基板領域裏面に形成される金属膜をさらに備える、請求項1または2に記載の半導体装置。
- 前記アノードは、さらに、前記金属膜に電気的に接続され、前記半導体装置を載置するとともに前記共通接地電圧を伝達するリードフレームをさらに備える、請求項5記載の半導体装置。
- 前記半導体基板領域は、前記カソードとなる半導体領域との間のPN接合に逆バイアス電圧が印加されたときに形成される空乏層の幅の最大値とほぼ等しい膜厚を有する、請求項1から4のいずれか1項に記載の半導体装置。
- 前記高耐圧ダイオードは、前記半導体基板領域と前記金属膜との間に形成され、前記半導体基板領域よりも高濃度の第1導電型の第4の半導体領域をさらに備える、請求項5または6に記載の半導体装置。
- 前記半導体基板領域の膜厚は、前記第4の半導体領域が設けられない場合に前記高耐圧ダイオードのカソードとなる半導体領域との間のPN接合に逆バイアス電圧が印加されるときに形成される空乏層の最大幅の1/2倍から2/3倍の間の膜厚に設定される、請求項8記載の半導体装置。
- 高電位側および低電位側パワーデバイスを駆動する半導体装置であって、
前記低電位側パワーデバイスを駆動する低電位側回路が配置される低電位領域と、
前記低電位領域と同一半導体基板領域上に形成され、高電圧が印加されて前記高電位側パワーデバイスを駆動する高電位側回路が配置される高電位領域、
前記高電位領域に配置され、前記高電位側および低電位側パワーデバイスの接続ノードに結合され、前記高電位側回路に対する仮想接地電位を供給する仮想接地電極パッド、
前記低電位側回路および高電位側回路に対し共通に接地電位を供給する共通接地電極パッド、および
前記半導体基板領域上に形成され、カソードが前記仮想接地電極パッドに電気的に接続され、アノードが前記共通接地電極パッドに電気的に接続される高耐圧ダイオードを備え、
前記高耐圧ダイオードは、
前記仮想接地電極パッドを構成する電極配線に接するように前記半導体基板領域上に形成され、前記仮想接地電極パッドの電極配線と電気的に接続され、前記高耐圧ダイオードのカソードとなる第1導電型の第1の半導体領域を備え、前記第1の半導体領域は前記仮想接地電極パッドの電極下部の少なくとも1つの領域において互いにスリット領域により分離され、
前記スリット領域において前記半導体基板領域が前記仮想接地電極配線と電気的に接続され、
前記半導体基板領域が前記高耐圧ダイオードのアノードとなる、半導体装置。 - 高電位側および低電位側パワーデバイスを駆動する半導体装置であって、
前記低電位側パワーデバイスを駆動する低電位側回路が配置される低電位領域と、
前記低電位領域と同一半導体基板領域上に形成され、高電圧が印加されて前記高電位側パワーデバイスを駆動する高電位側回路が配置される高電位領域、
前記高電位領域に配置され、前記高電位側および低電位側パワーデバイスの接続ノードに結合され、前記高電位側回路に対する仮想接地電位を供給する仮想接地電極パッド、
前記低電位側回路および高電位側回路に対し共通に接地電位を供給する共通接地電極パッド、および
前記半導体基板領域上に形成され、カソードが前記仮想接地電極パッドに電気的に接続され、アノードが前記共通接地電極パッドに電気的に接続される高耐圧ダイオードを備え、
前記半導体基板領域は第1の導電型を有し、
前記高耐圧ダイオードは、
前記半導体基板領域上に前記高電位領域を囲むように形成され、前記高耐圧ダイオードのカソードとなる第2導電型の第1の半導体領域と、
前記第1の半導体領域上に前記高電位領域を囲むように形成され、前記第1の半導体領域と電気的に接続されてカソード電極となる金属膜と、
前記金属膜下部に前記半導体基板領域に内部まで到達するように形成され、前記カソードとなる前記第1の半導体領域より高不純物濃度の第2の半導体領域と、
前記第1の半導体領域を囲むように形成されるとともに前記半導体基板領域に到達するように形成され、前記金属膜の配置領域と離れて配置され前記高耐圧ダイオードのアノードとなる第1導電型の第3の半導体領域とを備え、
前記第1および第2の半導体領域は、前記高電位側回路のハイ側電源電圧が印加される第2導電型の半導体領域と離れて配置される、半導体装置。 - 高電位側および低電位側パワーデバイスを駆動する半導体装置であって、
前記低電位側パワーデバイスを駆動する低電位側回路が配置される低電位領域と、
前記低電位領域と同一半導体基板領域上に形成され、高電圧が印加されて前記高電位側パワーデバイスを駆動する高電位側回路が配置される高電位領域、
前記高電位領域に配置され、前記高電位側および低電位側パワーデバイスの接続ノードに結合され、前記高電位側回路に対する仮想接地電位を供給する仮想接地電極パッド、
前記低電位側回路および高電位側回路に対し共通に接地電位を供給する共通接地電極パッド、および
前記半導体基板領域上に形成され、カソードが前記仮想接地電極パッドに電気的に接続され、アノードが前記共通接地電極パッドに電気的に接続される高耐圧ダイオードを備え、
前記高耐圧ダイオードは、前記仮想接地電極パッドを構成する電極配線に接して前記半導体基板領域上に形成され、前記仮想接地電極パッドの電極配線と電気的に接続されて前記高耐圧ダイオードのカソードとなる第1導電型の第1の半導体領域と、
前記第1の半導体領域下部に前記半導体基板領域内部にまで到達するように形成される第1導電型の前記第1の半導体領域よりも高濃度の第1の半導体領域を備え、
前記半導体基板領域が第2導電型を有し、かつ前記高耐圧ダイオードのアノードとなる、半導体装置。 - 高電位側および低電位側パワーデバイスを駆動する半導体装置であって、
前記低電位側パワーデバイスを駆動する低電位側回路が配置される低電位領域と、
前記低電位領域と同一半導体基板領域上に形成され、高電圧が印加されて前記高電位側パワーデバイスを駆動する高電位側回路が配置される高電位領域、
前記高電位領域に配置され、前記高電位側および低電位側パワーデバイスの接続ノードに結合され、前記高電位側回路に対する仮想接地電位を供給する仮想接地電極パッド、
前記低電位側回路および高電位側回路に対し共通に接地電位を供給する共通接地電極パッド、および
前記半導体基板領域上に形成され、カソードが前記仮想接地電極パッドに電気的に接続され、アノードが前記共通接地電極パッドに電気的に接続される高耐圧ダイオードを備え、
前記高耐圧ダイオードは、
前記仮想接地電極パッドを構成する電極配線に接して前記半導体基板領域上に形成され、前記仮想接地電極パッドの電極配線と電気的に接続されて前記高耐圧ダイオードのカソードとなる第1導電型の第1の半導体領域と、
前記第1の半導体領域に電気的に接続されるように形成されてカソード電極および前記仮想接地電極パッドとして機能する金属膜とを備え、
前記半導体基板領域が第2導電型を有して前記高耐圧ダイオードのアノードとなり、
前記第1の半導体領域は、前記高電位側回路のハイ側電源電圧が印加される第1導電型の高電位半導体領域と離れて配置され、
前記金属膜は前記高電位半導体領域上にまで絶縁膜を介して配置される部分を有する、半導体装置。
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TWI437688B (zh) | 2014-05-11 |
US8264057B2 (en) | 2012-09-11 |
DE102010008617A1 (de) | 2010-12-09 |
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