JP6228428B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6228428B2 JP6228428B2 JP2013225360A JP2013225360A JP6228428B2 JP 6228428 B2 JP6228428 B2 JP 6228428B2 JP 2013225360 A JP2013225360 A JP 2013225360A JP 2013225360 A JP2013225360 A JP 2013225360A JP 6228428 B2 JP6228428 B2 JP 6228428B2
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- 101100074059 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) YKU80 gene Proteins 0.000 description 33
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- 239000004020 conductor Substances 0.000 description 1
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- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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Description
図10は、第2の実施形態に係る半導体装置SDの構成を説明するための断面図であり、第1の実施形態における図3に対応している。本実施形態に係る半導体装置SDは、第3の高濃度第2導電型領域AFを有している点を除いて、第1の実施形態に係る半導体装置SDと同様の構成である。
図11は、第3の実施形態に係る半導体装置SDの構成を説明するための断面図であり、1の実施形態における図3に対応している。本実施形態に係る半導体装置SDは、以下の点を除いて、第2の実施形態に係る半導体装置SDと同様の構成である
BDF 埋込拡散層
BIDF 下部
BSC 容量素子
BSE 基板
CG 第1導電膜
CGINS 第1絶縁層
CNT1 コンタクト
CNT2 コンタクト
CON1 第1コンタクト
CON2 第2コンタクト
CON3 第3コンタクト
CON4 第4コンタクト
DCNT コンタクト
DF1 拡散層
DF2 拡散層
DIO ダイオード
DR ドレイン
DRE ドレイン電極
EI1 素子分離膜
EI2 素子分離膜
EL1 電極
EPI エピタキシャル層
FCNT1 コンタクト
FECNT コンタクト
FPE フィールドプレート電極
FP1 フィールドプレート電極
GCNT コンタクト
GE ゲート電極
GND 電力用接地配線
GP ゲートプレート電極
HDC ハイサイド駆動回路
HDF1 第1の高濃度第2導電型領域
HDF2 第2の高濃度第2導電型領域
HIN 制御信号
HM 第1トランジスタ
HRD 整流素子
HSR 第1回路領域
IDF 第1導電型領域
INSL1 層間絶縁膜
LD 負荷
LDC ローサイド駆動回路
LDF 第2導電型層
LDR1 ドリフト領域
LDR2 第2導電型層
LGC 信号処理回路
LM 第2トランジスタ
LSC レベルシフト回路
LSR 第2回路領域
MOSFET ローサイド
OPC 電力制御回路
PCC 電圧制御回路
SCNT コンタクト
SD 半導体装置
SO ソース
SOE ソース電極
SPR 分離領域
SUB 基板
TR 接続用トランジスタ
VINC1 電源配線
VINC2 電源配線
Claims (7)
- 第1導電型の基板と、
前記基板に形成され、電源電位が第1電圧である第1回路が形成されている第1回路領域と、
前記第1回路領域を囲んでいる分離領域と、
前記基板に形成され、平面視で前記分離領域の外側に位置し、電源電位が前記第1電圧よりも低い第2電圧である第2回路が形成されている第2回路領域と、
を備え、
前記分離領域は、
前記基板に形成された第2導電型領域と、
前記第2導電型領域に接続した第1の高濃度第2導電型領域と、
前記第2導電型領域に接続し、前記第1の高濃度第2導電型領域から離れている第2の高濃度第2導電型領域と、
前記基板に形成され、前記第1の高濃度第2導電型領域と前記第2の高濃度第2導電型領域の間に位置し、かつ前記第2の高濃度第2導電型領域から離れている素子分離膜と、
前記基板のうち前記第2の高濃度第2導電型領域と前記素子分離膜の間に位置する領域の上に形成された第1絶縁膜と、
前記第1絶縁膜を覆う第1導電膜と、
前記第1の高濃度第2導電型領域に接続している第1コンタクトと、
前記第2の高濃度第2導電型領域に接続している第2コンタクトと、
前記第1導電膜に接続している第3コンタクトと、
を備え、
前記第1コンタクト、前記第2コンタクト、及び前記第3コンタクトは、互いに分離しており、
前記第3コンタクトに印加される電圧を制御する電圧制御回路を備え、
前記第2導電型領域と前記第1の高濃度第2導電型領域は、pn接合が介在しない電流経路によって互いに接続しており、
前記第2導電型領域と前記第2の高濃度第2導電型領域は、pn接合が介在しない電流経路によって互いに接続している半導体装置。 - 請求項1に記載の半導体装置において、
前記第2コンタクトには前記第2電圧が印加される半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体装置は電力制御回路とともに使用され、
前記電力制御回路は、
電力用電源配線と前記電力制御回路の出力端子とを接続する第1トランジスタと、
電力用接地配線と前記出力端子とを接続する第2トランジスタと、
一方の端子が前記出力端子に接続している容量素子と、
を備え、
前記半導体装置は、
前記第1トランジスタの第1ゲート電極に接続しており、前記第1回路である第1駆動回路と、
前記第2トランジスタの第2ゲート電極に接続しており、前記第2回路である第2駆動回路と、
を備え、
前記第1コンタクトは、前記容量素子の他方の端子に接続しており、
前記電圧制御回路及び前記第1駆動回路、又は前記電圧制御回路及び前記第2駆動回路には同一の制御信号が入力される半導体装置。 - 請求項1に記載の半導体装置において、
前記第1の高濃度第2導電型領域及び前記第2の高濃度第2導電型領域は、前記第2導電型領域に形成されている半導体装置。 - 請求項4に記載の半導体装置において、
平面視において前記第2の高濃度第2導電型領域の隣に位置しており、前記第2導電型領域を上下に貫いている第1導電型領域と、
前記第1導電型領域に接続する第4コンタクトと、
を備え、
前記第1導電型領域の下部は、前記第2の高濃度第2導電型領域の下方に向けて張り出している半導体装置。 - 請求項4に記載の半導体装置において、
前記第2導電型領域に形成され、前記第1絶縁膜の下に位置する第3の高濃度第2導電型領域を備える半導体装置。 - 請求項1に記載の半導体装置において、
前記第2導電型領域を上下に貫いている第1導電型領域と、
前記第1導電型領域に接続する第4コンタクトと、
前記第1絶縁膜の下に位置する第3の高濃度第2導電型領域と、
を備え、
前記第2の高濃度第2導電型領域は、前記第1導電型領域に形成されており、
前記第3の高濃度第2導電型領域は、前記第1導電型領域から前記第2導電型領域にかけて形成されており、
前記第3の高濃度第2導電型領域は、前記第2の高濃度第2導電型領域よりも浅く、
前記第2導電型領域と前記第2の高濃度第2導電型領域は、前記第3の高濃度第2導電型領域を介して互いに接続している半導体装置。
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US14/517,657 US9287256B2 (en) | 2013-10-30 | 2014-10-17 | Semiconductor device including a separation region formed around a first circuit region |
CN201410594450.8A CN104600046B (zh) | 2013-10-30 | 2014-10-29 | 半导体器件 |
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