JP6210913B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6210913B2 JP6210913B2 JP2014059016A JP2014059016A JP6210913B2 JP 6210913 B2 JP6210913 B2 JP 6210913B2 JP 2014059016 A JP2014059016 A JP 2014059016A JP 2014059016 A JP2014059016 A JP 2014059016A JP 6210913 B2 JP6210913 B2 JP 6210913B2
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Description
図1は、第1の実施形態に係る半導体装置SDが用いられる電気機器の機能ブロック図である。本実施形態に係る半導体装置SDは、電力制御回路OPCに制御信号を印加するための装置である。電力制御回路OPCは、負荷LD、例えばモータに入力する電力を制御する。すなわち半導体装置SDは、電力制御回路OPCを介して負荷LDを制御している。
図17は、第2の実施形態に係る半導体装置SDの構成を示す平面図であり、第1の実施形態の図2に対応する。本実施形態に係る半導体装置SDは、以下の点を除いて第1の実施形態に係る半導体装置SDと同様の構成である。
図18は、第3の実施形態に係る半導体装置SDの構成を示す平面図の一部の領域を拡大した図であり、第1の実施形態の図3に対応する。図19〜図24は、図18のA−A´〜F−F´断面図であり、第1の実施形態の図4〜図9に対応する。本実施形態に係る半導体装置SDは、以下の点を除いて第1の実施形態に係る半導体装置SDと同様の構成である。
図25は、第4の実施形態に係る半導体装置SDの構成を示す平面図であり、第1の実施形態の図2に対応する。図26は、図25の点線αで囲んだ領域を拡大した図であり、第1の実施形態の図3に対応する。図27〜図32は、図26のA−A´〜F−F´断面図であり、第1の実施形態の図4〜図9に対応する。図33は、図26のG−G´断面図である。図34は、図25の点線βで囲んだ領域を拡大した図である。図35は、図34のA−A´断面図である。本実施形態に係る半導体装置SDは、以下の点を除いて第1の実施形態に係る半導体装置SDと同様の構成である。
BSE 基板
CF 導電膜
CCNT コンタクト
CNT1〜CNT9 コンタクト
DCNT コンタクト
DL 絶縁層
DR ドレイン
EPI 半導体層
EL1〜EL3 電極
DRE1,DRE2 ドレイン電極
EI 素子分離膜
FCNT1 コンタクト
FECNT1,FECNT2 コンタクト
FP1,FP2 フィールドプレート
FPE1〜FPE3 フィールドプレート電極
GCNT コンタクト
GDR ガードリング
GE ゲート電極
GP ゲートプレート電極
HDC ハイサイド駆動回路
HDF1〜HDF3 高濃度層
HM ハイサイドMOSトランジスタ
HSR 第1回路領域
IDF 第2導電型領域
INSL1〜INSL3 層間絶縁膜
LD 負荷
LDC ローサイド駆動回路
LDF 第1導電型層
LDR ドリフト領域
LGC 制御回路
LM ローサイドMOSトランジスタ
LSC レベルシフト回路
LSR 第2回路領域
OPC 電力制御回路
PMC パルス発生回路
SBP1〜SBP3 電極
SCNT コンタクト
SD 半導体装置
SIL 半絶縁性膜
SO ソース
SOE ソース電極
SPR 分離領域
SR 封止樹脂
SUB 基板
TR トランジスタ
Claims (8)
- 基板と、
前記基板に形成され、電源電位が第1電圧である第1回路が形成されている第1回路領域と、
前記第1回路領域を囲んでいる分離領域と、
前記基板に形成され、平面視で前記分離領域の外側に位置し、電源電位が前記第1電圧よりも低い第2電圧である第2回路が形成されている第2回路領域と、
前記分離領域に位置し、前記第2回路を前記第1回路に接続し、ソース及びドレインが第1導電型であるトランジスタと、
を備え、
前記分離領域は、
前記基板に形成された素子分離膜と、
平面視で前記素子分離膜と重なっており、前記第1回路領域の縁に沿う方向に、繰り返し設けられた第1フィールドプレートと、
前記第1フィールドプレートの上方に設けられた複数の導電膜と、
前記基板に設けられ、平面視で前記素子分離膜と重なっており、かつ前記トランジスタの周囲に位置する第2導電型領域と、
前記第2導電型領域を介して前記トランジスタのソース又はドレインと逆側に位置する第1導電型領域と、
を有し、
前記第2導電型領域のうち前記第1回路領域の側から前記第2回路領域の側に向かって延在している部分と前記基板に形成された素子分離膜と平面視で重なる領域において、
前記第1フィールドプレートと前記複数の導電膜は、平面視において、前記第1回路領域の側から前記第2回路領域の側に向かって交互に設けられており、
前記第1フィールドプレートの電位と前記複数の導電膜の電位は、前記第1回路領域から前記第2回路領域に近づくにしたがって低下しており、
前記複数の導電膜のうちの少なくとも一の導電膜は、
平面視で前記第2回路領域の側で当該導電膜に隣接する前記第1フィールドプレートの電位以下の電位を有しており、
前記第2導電型領域の少なくとも一部を前記第2導電型領域の延在方向に沿って隙間なく覆っており、
前記導電膜は、平面視で前記第1回路領域の側で当該導電膜に隣接する前記第1フィールドプレート、及び平面視で前記第2回路領域の側で当該導電膜に隣接する前記第1フィールドプレートのいずれか一方と、ビアを介して電気的に接続している半導体装置。 - 請求項1に記載の半導体装置において、
前記トランジスタのドレイン電極の電圧又は前記第1回路領域内の他の電極の電圧が、前記第1回路領域の側の前記第1フィールドプレートに印加されており、
接地電位又は前記第2電圧が、前記第2回路領域の側の前記第1フィールドプレートに印加されており、
前記ドレイン電極の前記電圧が印加されている前記第1フィールドプレートと前記接地電位又は前記第2電圧が印加されている前記第1フィールドプレートの間において、
前記第1フィールドプレートの電位と前記複数の導電膜の電位は、前記接地電位又は前記第2電圧以上かつ前記ドレイン電極の前記電圧以下である半導体装置。 - 請求項1に記載の半導体装置において、
前記導電膜は、平面視で前記第2回路領域の側で当該導電膜に隣接する前記第1フィールドプレートと前記ビアを介して電気的に接続している半導体装置。 - 請求項1に記載の半導体装置において、
互いに隣接する少なくとも2つの前記導電膜が、
互いに繋がっており、
当該導電膜と平面視で重なる前記第1フィールドプレートとビアを介して電気的に接続しており、
当該導電膜と接続している前記第1フィールドプレートと、前記第1回路領域の側で当該第1フィールドプレートと隣接する前記第1フィールドプレートとの間の前記第2導電型領域の少なくとも一部を前記第2導電型領域の延在方向に沿って隙間なく覆っている半導体装置。 - 請求項1に記載の半導体装置において、
前記第1フィールドプレートは、
前記第1回路領域の縁に沿う方向に、折り返されながら又はスパイラル状に、繰り返し設けられており、
最も内周側の周で前記トランジスタのドレイン電極又は前記第1回路領域内の他の電極に電気的に接続されており、かつ、
最も外周側の周で接地電位又は前記第2回路に接続されている半導体装置。 - 請求項1に記載の半導体装置において、
隣接する前記第1フィールドプレートは、電気的に互いに浮遊している半導体装置。 - 請求項1に記載の半導体装置において、
前記複数の導電膜は、
互いに離間しており、
半絶縁性膜で覆われている半導体装置。 - 請求項1に記載の半導体装置において、
前記複数の導電膜は、前記第1フィールドプレートの上側に位置する第2フィールドプレートの一部であり、
前記第2フィールドプレートは、
平面視で前記素子分離膜と重なっており、前記第1回路領域の縁に沿う方向に、折り返されながら又はスパイラル状に、繰り返し設けられており、
最も内周側の周で前記トランジスタのドレイン電極又は前記第1回路領域内の他の電極に電気的に接続されており、かつ、
最も外周側の周で接地電位又は前記第2回路に接続されている半導体装置。
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