CN111312707B - 一种低比导通电阻的功率半导体器件 - Google Patents
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Abstract
本发明提供一种低比导通电阻(Ron,sp)的功率半导体器件,包括功率器件、瞬态电压抑制器(TVS);其中功率器件的高压端电极与瞬态电压抑制器的阳极电极通过金属相连,功率器件的低压端电极与瞬态电压抑制器的阴极电极通过金属相连;本发明可以利用瞬态电压抑制器的钳位特性,降低对于功率器件的耐压(BV)需求,从而由于Ron,sp和BV之间的极限关系,可以进一步降低器件的比导通电阻,从而降低器件的功率损耗。
Description
技术领域
本发明属于电子科学与技术领域,主要涉及半导体技术,具体的说是关于功率半导体器件。
背景技术
高压功率器件是高压功率集成电路发展必不可少的部分。由于功率器件所应用的电路中通常带有电感性负载,而当电感性负载的电流有突然的变化时,电感两端会产生突变电压,可能会破坏其他元件。因此功率器件的击穿电压要求一般会大大高于其工作电压。高压功率器件要求具有高的击穿电压,低的导通电阻和低的开关损耗。高压功率器件为了实现高的击穿电压,要求其用于承担耐压的漂移区具有低掺杂浓度,但为了满足器件低导通电阻,又要求作为电流通道的漂移区具有高掺杂浓度。这一矛盾关系限制了高压功率器件在高压功率集成电路中的应用,尤其是在要求低导通损耗和小芯片面积的电路中。
瞬态电压抑制器(TVS:Transient Voltage Suppressor)是普遍使用的一种新型高效电路保护器件,它具有极快的响应时间(亚纳秒级)和相当高的浪涌吸收能力。当它的两端经受瞬间的高能量冲击时,TVS能以极高的速度把两端间的阻抗值由高阻抗变为低阻抗,以吸收一个瞬间大电流,把它的两端电压钳制在一个预定的数值上,从而保护后面的电路元件不受瞬态高压尖峰脉冲的冲击。
发明内容
本发明要解决的问题是:降低功率器件在实际应用中的耐压要求,随之降低其比导通电阻。
为实现上述发明目的,本发明技术方案如下:
一种低比导通电阻的功率半导体器件,包括:功率器件M1,其中包括:栅电极1、漏电极2、体电极3,源电极4和寄生体二极管5,其中体电极3和源电极4短接;瞬态电压抑制器T1,其中包括阳极6和阴极7;其中功率器件的漏极2与瞬态电压抑制器TVS的阳极6通过金属相连构成高压端电极8,功率器件的源极4与TVS的阴极7通过金属相连构成低压端电极9。
作为优选方式,所述器件包括P型衬底104、位于P型衬底104上方左侧的第一P型阱区103、位于第一P型阱区103右侧且相切的第一N型漂移区114、位于第一N型漂移区114右侧的TVS部分;位于第一P型阱区103内部上方的第一P+接触区101和第一N+接触区111、位于第一P+接触区101上的第一体电极金属151、位于第一N+接触区111上的第一源电极金属152、位于第一N型漂移区114内部上方右侧的第二N+接触区112、位于第二N+接触区112上的第一漏电极金属153、位于第二N+接触区112左侧且部分在第一N型漂移区114内部的第一场氧区141、位于P型衬底104上表面的第一栅氧化层140,其中第一栅氧化层140的左边缘与第一N+接触区111右边缘相切,第一栅氧化层140的右边缘与第一场氧区141相连;位于第一栅氧化层140和第一场氧区141上表面的第一多晶硅栅电极150;其中各电极金属分别与下方的重掺杂接触区形成欧姆接触,其中第一体电极金属151、第一源电极金属152和TVS部分的第一阴极金属通过金属相连,构成第一低压端电极131;第一漏电极金属153和TVS部分的第一阳极金属通过金属相连,构成第一高压端电极132。
作为优选方式,TVS部分包括:位于第一N型漂移区114右侧的第一N型阱区115、位于第一N型阱区115内部上方的第三N+接触区113和第二P+接触区102、位于第三N+接触区113上的第一阳极金属154、位于第二P+接触区102上的第一阴极金属155,其中各电极金属分别与下方的重掺杂接触区形成欧姆接触;位于第三N+接触区113和第二P+接触区102之间且部分在第一N型阱区115内部的第二场氧区142。
作为优选方式,第一阴极金属155不仅与下方的第二P+接触区102形成欧姆接触,而且同时与第一N型阱区115形成肖特基接触。
作为优选方式,TVS部分包括:第二N型阱区118、位于第二N型阱区118内部上方的第三P+接触区105和第四N+接触区116,其中第三P+接触区105的左边缘与第四N+接触区116的右边缘相切、位于第二N型阱区118右侧且与第二N型阱区118右边缘相切的第二P型阱区107、位于第二P型阱区107内部上方的第四P+接触区106和第五N+接触区117,其中第四P+接触区106的左边缘与第五N+接触区117的右边缘相切;其中第一阳极金属154与下方的第三P+接触区105和第四N+接触区116形成欧姆接触,第一阴极金属155与下方的第四P+接触区106和第五N+接触区117形成欧姆接触。
作为优选方式,所述器件包括:位于第二P型阱区107内部左侧上方的第一P型注入区108,且第一P型注入区108的左边缘与第二P型阱区107的左边缘相切,第一P型注入区108的右边缘在第五N+接触区117的左侧;位于第二N型阱区118和第一P型注入区108交界处上方的第一N型触发区119,其中第一N型触发区119的左边缘在第二N型阱区118内部,且在第三P+接触区105右侧;第一N型触发区119的右边缘在第一P型注入区108内部;第一N型触发区119的深度比第一P型注入区108浅。
作为优选方式,所述器件包括:第二高压端电极232、与第二高压端电极232上表面相切的第一N+衬底214、与第一N+衬底214上表面相切的第一N型外延层213;位于第一N型外延层213内部上方的第三P型阱区204、第四P型阱区205和第三N型阱区215,其中第四P型阱区205位于第三P型阱区204右侧,第三N型阱区215位于第四P型阱区205右侧,且三者互不相连;位于第三P型阱区204内部上方的第五P+接触区201和第六N+接触区211,位于第五P+接触区201上方的第二体电极金属251,位于第六N+接触区211上方的第二源电极金属252,其中第五P+接触区201的右边缘与第六N+接触区211的左边缘相切;位于第四P型阱区205内部上方的第六P+接触区202和第七N+接触区212,位于第六P+接触区202上方的第三体电极金属254,位于第七N+接触区212上方的第三源电极金属253,其中第六P+接触区202的左边缘与第七N+接触区212的右边缘相切;位于第三N型阱区215内部上方的第七P+接触区203,位于第七P+接触区203上方的第二阴极金属255;第一N型外延层213外侧上表面的第二栅氧化层240,且第二栅氧化层240的左边缘与第六N+接触区211的右边缘相切,第二栅氧化层240的右边缘与第七N+接触区212的左边缘相切;位于第二栅氧化层240上的第二多晶硅栅电极250,且第二多晶硅栅电极250左右边缘均与第二栅氧化层240相同;其中各电极金属分别与下方的重掺杂接触区形成欧姆接触;第二体电极金属251、第二源电极金属252、第三源电极金属253、第三体电极金属254和第二阴极金属255通过金属相连构成第二低压端电极231。
作为优选方式,第二阴极金属255不仅与下方的第七P+接触区203形成欧姆接触,而且同时与第三N型阱区215形成肖特基接触。
作为优选方式,第三N型阱区215替换成P型阱区,通过调整其结深和/或掺杂浓度实现所需的钳位电压。
作为优选方式,所述功率器件中的N型改成P型,P型改成N型,功率器件的高压端电极与瞬态电压抑制器的阳极电极相连,功率器件的低压端电极与瞬态电压抑制器的阴极电极相连。
作为优选方式,所述功率器件选自LDMOS、VDMOS、JFET、SIT器件。
作为优选方式,所述功率器件和瞬态电压抑制器的衬底材料选自体硅或SOI衬底材料。
本发明的有益效果为:本发明提出具有低比导通电阻的功率半导体器件,通过功率器件与瞬态电压抑制器的集成,从而利用瞬态电压抑制器的钳位特性,降低对于功率器件的耐压(BV)需求,从而由于Ron,sp和BV之间的关系,可以进一步降低器件的比导通电阻,从而降低器件的功率损耗。
附图说明
图1(a)为传统功率器件示意图;
图1(b)为传统横向功率器件的剖面示意图;
图1(c)为传统纵向功率器件的剖面示意图;
图2为实施例1的示意图;
图3(a)为传统功率器件和实施例1的对比图;
图3(b)为实施例1的原理示意图;
图4为实施例2的剖面示意图;
图5为实施例3的剖面示意图;
图6为实施例4的剖面示意图;
图7为实施例5的剖面示意图;
图8为实施例6的剖面示意图;
图9为实施例7的剖面示意图;
M1为功率器件,1为栅电极,2为漏电极,3为体电极,4为源电极,5为寄生体二极管;T1为瞬态电压抑制器。6为阳极,7为阴极;8为高压端电极,9为低压端电极;101为第一P+接触区,102为第二P+接触区,103为第一P型阱区,104为P型衬底,105为第三P+接触区,106为第四P+接触区,107为第二P型阱区,108为第一P型注入区,111为第一N+接触区,112为第二N+接触区,113为第三N+接触区,114为第一N型漂移区,115为第一N型阱区,116为第四N+接触区,117为第五N+接触区,118为第二N型阱区,119为第一N型触发区,131为第一低压端电极,132为第一高压端电极,140为第一栅氧化层,141为第一场氧区,142为第二场氧区,150为第一多晶硅栅电极,151为第一体电极金属,152为第一源电极金属,153为第一漏电极金属,154为第一阳极金属,155为第一阴极金属;201为第五P+接触区,202为第六P+接触区,203为第七P+接触区,204为第三P型阱区,205为第四P型阱区,211为第六N+接触区,212为第七N+接触区,213为第一N型外延层,214为第一N+衬底,215为第三N型阱区,231为第二低压端电极,232为第二高压端电极,240为第二栅氧化层,250为第二多晶硅栅电极,251为第二体电极金属,252为第二源电极金属,253为第三源电极金属,254为第三体电极金属,255为第二阴极金属。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
实施例1
如图2所示,一种低比导通电阻的功率半导体器件,包括:功率器件M1,其中包括:栅电极1、漏电极2、体电极3,源电极4和寄生体二极管5,其中体电极3和源电极4短接;瞬态电压抑制器T1,其中包括阳极6和阴极7;其中功率器件的漏极2与瞬态电压抑制器TVS的阳极6通过金属相连构成高压端电极8,功率器件的源极4与TVS的阴极7通过金属相连构成低压端电极9。
本例的工作原理为:
功率器件所应用的电路中通常带有电感性负载,而当电感性负载的电流有突然的变化时,电感两端会产生突变电压,可能会破坏其他元件。因此功率器件的击穿电压要求一般会大大高于其工作电压。功率器件需要实现高的击穿电压,就要求其用于承担耐压的漂移区具有低掺杂浓度,但为了满足器件低导通电阻,又要求作为电流通道的漂移区具有高掺杂浓度。从而功率器件的击穿电压和比导通电阻两者间存在一种极限关系。如图1(a)所示,功率器件中存在寄生体二极管。如图1(b)所示,传统横向功率器件LDMOS的体二极管由P+接触区、P型阱区、N型漂移区和N+接触区构成;如图1(c)所示,传统纵向功率器件VDMOS的体二极管由P+接触区、P型阱区、N型外延层和N+衬底构成。由此可知,寄生体二极管的触发电压还是由N型漂移区或N型外延层与P型阱区构成的反偏PN结决定,因此寄生体二极管的触发电压和功率器件的耐压基本一致,并不能起到钳位电压的作用,即对于功率器件的耐压要求并没有改变。本发明将瞬态电压抑制器与功率器件集成在一起,其中不同于体二极管的是瞬态电压抑制器的触发电压与功率器件耐压没有直接关联,并且可以根据需求调整,如图3(a)所示,当功率器件两端产生突变电压时,瞬态电压抑制器能极快地开启,并将两端电压钳位在一个预定的数值上;而当功率器件正常工作时,瞬态电压抑制器处于关闭状态,不会影响到功率器件的正常工作状态。如此一来,如图3(b)所示,功率器件的击穿电压需求可以适当下降,由于击穿电压和比导通电阻之间的极限关系,当击穿电压需求下降时,比导通电阻值也会同时下降,从而实现功率器件更低的功率损耗。另外,功率器件由于其电流能力的要求,一般面积较大,相较而言,集成瞬态电压抑制器所需的面积可以忽略。
实施例2
如图4所示,本实施例具体展示了一种横向功率器件与瞬态电压抑制器集成的剖面示意图,包括:P型衬底104、位于P型衬底104上方左侧的第一P型阱区103、与第一P型阱区103右侧的第一N型漂移区114、位于第一N型漂移区114右侧的第一N型阱区115、位于第一P型阱区103内部上方的第一P+接触区101和第一N+接触区111、位于第一P+接触区101上的第一体电极金属151、位于第一N+接触区111上的第一源电极金属152、位于第一N型漂移区114内部上方右侧的第二N+接触区112、位于第二N+接触区112上的第一漏电极金属153、位于第一N型阱区115内部上方的第三N+接触区113和第二P+接触区102、位于第三N+接触区113上的第一阳极金属154、位于第二P+接触区102上的第一阴极金属155、位于第二N+接触区112左侧且部分在第一N型漂移区114内部的第一场氧区141、位于第三N+接触区113和第二P+接触区102之间且部分在第一N型阱区115内部的第二场氧区142;位于P型衬底104上表面的第一栅氧化层140,其中第一栅氧化层140的左边缘与第一N+接触区111右边缘相切,第一栅氧化层140的右边缘与第一场氧区141相连;位于第一栅氧化层140和第一场氧区141上表面的第一多晶硅栅电极150;其中各电极金属分别与下方的重掺杂接触区形成欧姆接触,其中第一体电极金属151、第一源电极金属152和第一阴极金属155通过金属相连,构成第一低压端电极131;第一漏电极金属153和第一阳极金属154通过金属相连,构成第一高压端电极132。
实施例3
如图5所示,本实施例的器件结构和实施例2的区别在于:第一阴极金属155不仅与下方的第二P+接触区102形成欧姆接触,而且同时与第一N型阱区115形成肖特基接触。
实施例4
如图6所示,本实施例的器件结构和实施例2的区别在于:TVS部分包括:第二N型阱区118、位于第二N型阱区118内部上方的第三P+接触区105和第四N+接触区116,其中第三P+接触区105的左边缘与第四N+接触区116的右边缘相切、位于第二N型阱区118右侧且与第二N型阱区118右边缘相切的第二P型阱区107、位于第二P型阱区107内部上方的第四P+接触区106和第五N+接触区117,其中第四P+接触区106的左边缘与第五N+接触区117的右边缘相切;其中第一阳极金属154与下方的第三P+接触区105和第四N+接触区116形成欧姆接触,第一阴极金属155与下方的第四P+接触区106和第五N+接触区117形成欧姆接触。
实施例5
如图7所示,本实施例的器件结构和实施例4的区别在于:位于第二P型阱区107内部左侧上方的第一P型注入区108,且第一P型注入区108的左边缘与第二P型阱区107的左边缘相切,第一P型注入区108的右边缘在第五N+接触区117的左侧;位于第二N型阱区118和第一P型注入区108交界处上方的第一N型触发区119,其中第一N型触发区119的左边缘在第二N型阱区118内部,且在第三P+接触区105右侧;第一N型触发区119的右边缘在第一P型注入区108内部;第一N型触发区119的深度比第一P型注入区108浅。
实施例6
如图8所示,本实施例具体展示了一种纵向功率器件与瞬态电压抑制器集成的剖面示意图,包括:第二高压端电极232、与第二高压端电极232上表面相切的第一N+衬底214、与第一N+衬底214上表面相切的第一N型外延层213;位于第一N型外延层213内部上方的第三P型阱区204、第四P型阱区205和第三N型阱区215,其中第四P型阱区205位于第三P型阱区204右侧,第三N型阱区215位于第四P型阱区205右侧,且三者互不相连;位于第三P型阱区204内部上方的第五P+接触区201和第六N+接触区211,位于第五P+接触区201上方的第二体电极金属251,位于第六N+接触区211上方的第二源电极金属252,其中第五P+接触区201的右边缘与第六N+接触区211的左边缘相切;位于第四P型阱区205内部上方的第六P+接触区202和第七N+接触区212,位于第六P+接触区202上方的第三体电极金属254,位于第七N+接触区212上方的第三源电极金属253,其中第六P+接触区202的左边缘与第七N+接触区212的右边缘相切;位于第三N型阱区215内部上方的第七P+接触区203,位于第七P+接触区203上方的第二阴极金属255;第一N型外延层213外侧上表面的第二栅氧化层240,且第二栅氧化层240的左边缘与第六N+接触区211的右边缘相切,第二栅氧化层240的右边缘与第七N+接触区212的左边缘相切;位于第二栅氧化层240上的第二多晶硅栅电极250,且第二多晶硅栅电极250左右边缘均与第二栅氧化层240相同;其中各电极金属分别与下方的重掺杂接触区形成欧姆接触;第二体电极金属251、第二源电极金属252、第三源电极金属253、第三体电极金属254和第二阴极金属255通过金属相连构成第二低压端电极231。
实施例7
如图9所示,本实施例的器件结构和实施例6的区别在于:第二阴极金属255不仅与下方的第七P+接触区203形成欧姆接触,而且同时与第三N型阱区215形成肖特基接触。
Claims (11)
1.一种低比导通电阻的功率半导体器件,其特征在于包括:功率器件M1,其中包括:栅电极(1)、漏电极(2)、体电极(3),源电极(4)和寄生体二极管(5),其中体电极(3)和源电极(4)短接;瞬态电压抑制器T1,其中包括阳极(6)和阴极(7);其中功率器件的漏极(2)与瞬态电压抑制器TVS的阳极(6)通过金属相连构成高压端电极(8),功率器件的源极(4)与TVS的阴极(7)通过金属相连构成低压端电极(9);
还包括:P型衬底(104)、位于P型衬底(104)上方左侧的第一P型阱区(103)、位于第一P型阱区(103)右侧且相切的第一N型漂移区(114)、位于第一N型漂移区(114)右侧的TVS部分;位于第一P型阱区(103)内部上方的第一P+接触区(101)和第一N+接触区(111)、位于第一P+接触区(101)上的第一体电极金属(151)、位于第一N+接触区(111)上的第一源电极金属(152)、位于第一N型漂移区(114)内部上方右侧的第二N+接触区(112)、位于第二N+接触区(112)上的第一漏电极金属(153)、位于第二N+接触区(112)左侧且部分在第一N型漂移区(114)内部的第一场氧区(141)、位于P型衬底(104)上表面的第一栅氧化层(140),其中第一栅氧化层(140)的左边缘与第一N+接触区(111)右边缘相切,第一栅氧化层(140)的右边缘与第一场氧区(141)相连;位于第一栅氧化层(140)和第一场氧区(141)上表面的第一多晶硅栅电极(150);其中各电极金属分别与下方的重掺杂接触区形成欧姆接触,其中第一体电极金属(151)、第一源电极金属(152)和TVS部分的第一阴极金属通过金属相连,构成第一低压端电极(131);第一漏电极金属(153)和TVS部分的第一阳极金属通过金属相连,构成第一高压端电极(132)。
2.根据权利要求1所述的一种低比导通电阻的功率半导体器件,其特征在于:TVS部分包括:位于第一N型漂移区(114)右侧的第一N型阱区(115)、位于第一N型阱区(115)内部上方的第三N+接触区(113)和第二P+接触区(102)、位于第三N+接触区(113)上的第一阳极金属(154)、位于第二P+接触区(102)上的第一阴极金属(155),其中各电极金属分别与下方的重掺杂接触区形成欧姆接触;位于第三N+接触区(113)和第二P+接触区(102)之间且部分在第一N型阱区(115)内部的第二场氧区(142)。
3.根据权利要求2所述的一种低比导通电阻的功率半导体器件,其特征在于:第一阴极金属(155)不仅与下方的第二P+接触区(102)形成欧姆接触,而且同时与第一N型阱区(115)形成肖特基接触。
4.根据权利要求1所述的一种低比导通电阻的功率半导体器件,其特征在于:TVS部分包括:第二N型阱区(118)、位于第二N型阱区(118)内部上方的第三P+接触区(105)和第四N+接触区(116),其中第三P+接触区(105)的左边缘与第四N+接触区(116)的右边缘相切、位于第二N型阱区(118)右侧且与第二N型阱区(118)右边缘相切的第二P型阱区(107)、位于第二P型阱区(107)内部上方的第四P+接触区(106)和第五N+接触区(117),其中第四P+接触区(106)的左边缘与第五N+接触区(117)的右边缘相切;其中第一阳极金属(154)与下方的第三P+接触区(105)和第四N+接触区(116)形成欧姆接触,第一阴极金属(155)与下方的第四P+接触区(106)和第五N+接触区(117)形成欧姆接触。
5.根据权利要求4所述的一种低比导通电阻的功率半导体器件,其特征在于包括:位于第二P型阱区(107)内部左侧上方的第一P型注入区(108),且第一P型注入区(108)的左边缘与第二P型阱区(107)的左边缘相切,第一P型注入区(108)的右边缘在第五N+接触区(117)的左侧;位于第二N型阱区(118)和第一P型注入区(108)交界处上方的第一N型触发区(119),其中第一N型触发区(119)的左边缘在第二N型阱区(118)内部,且在第三P+接触区(105)右侧;第一N型触发区(119)的右边缘在第一P型注入区(108)内部;第一N型触发区(119)的深度比第一P型注入区(108)浅。
6.根据权利要求1所述的一种低比导通电阻的功率半导体器件,其特征在于包括:第二高压端电极(232)、与第二高压端电极(232)上表面相切的第一N+衬底(214)、与第一N+衬底(214)上表面相切的第一N型外延层(213);位于第一N型外延层(213)内部上方的第三P型阱区(204)、第四P型阱区(205)和第三N型阱区(215),其中第四P型阱区(205)位于第三P型阱区(204)右侧,第三N型阱区(215)位于第四P型阱区(205)右侧,且三者互不相连;位于第三P型阱区(204)内部上方的第五P+接触区(201)和第六N+接触区(211),位于第五P+接触区(201)上方的第二体电极金属(251),位于第六N+接触区(211)上方的第二源电极金属(252),其中第五P+接触区(201)的右边缘与第六N+接触区(211)的左边缘相切;位于第四P型阱区(205)内部上方的第六P+接触区(202)和第七N+接触区(212),位于第六P+接触区(202)上方的第三体电极金属(254),位于第七N+接触区(212)上方的第三源电极金属(253),其中第六P+接触区(202)的左边缘与第七N+接触区(212)的右边缘相切;位于第三N型阱区(215)内部上方的第七P+接触区(203),位于第七P+接触区(203)上方的第二阴极金属(255);第一N型外延层(213)外侧上表面的第二栅氧化层(240),且第二栅氧化层(240)的左边缘与第六N+接触区(211)的右边缘相切,第二栅氧化层(240)的右边缘与第七N+接触区(212)的左边缘相切;位于第二栅氧化层(240)上的第二多晶硅栅电极(250),且第二多晶硅栅电极(250)左右边缘均与第二栅氧化层(240)相同;其中各电极金属分别与下方的重掺杂接触区形成欧姆接触;第二体电极金属(251)、第二源电极金属(252)、第三源电极金属(253)、第三体电极金属(254)和第二阴极金属(255)通过金属相连构成第二低压端电极(231)。
7.根据权利要求6所述的一种低比导通电阻的功率半导体器件,其特征在于:第二阴极金属(255)不仅与下方的第七P+接触区(203)形成欧姆接触,而且同时与第三N型阱区(215)形成肖特基接触。
8.根据权利要求6所述的一种低比导通电阻的功率半导体器件,其特征在于:第三N型阱区(215)替换成P型阱区,通过调整其结深和/或掺杂浓度实现所需的钳位电压。
9.根据权利要求1~8任意一项所述的一种低比导通电阻的功率半导体器件,其特征在于:所述功率器件中的N型改成P型,P型改成N型,功率器件的高压端电极与瞬态电压抑制器的阳极电极相连,功率器件的低压端电极与瞬态电压抑制器的阴极电极相连。
10.根据权利要求1所述的一种低比导通电阻的功率半导体器件,其特征在于:所述功率器件选自LDMOS、VDMOS、JFET、SIT器件。
11.根据权利要求1~8任意一项所述的一种低比导通电阻的功率半导体器件,其特征在于:所述功率器件和瞬态电压抑制器的衬底材料选自体硅或SOI衬底材料。
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