JP4519442B2 - Mosトランジスター及びその製造方法 - Google Patents
Mosトランジスター及びその製造方法 Download PDFInfo
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- JP4519442B2 JP4519442B2 JP2003358405A JP2003358405A JP4519442B2 JP 4519442 B2 JP4519442 B2 JP 4519442B2 JP 2003358405 A JP2003358405 A JP 2003358405A JP 2003358405 A JP2003358405 A JP 2003358405A JP 4519442 B2 JP4519442 B2 JP 4519442B2
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- insulating film
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- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 239000000758 substrate Substances 0.000 claims description 50
- 239000004065 semiconductor Substances 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 27
- 125000006850 spacer group Chemical group 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 101100520660 Drosophila melanogaster Poc1 gene Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 101100520662 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) PBA1 gene Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
Description
図1は本発明の第1実施例によるN型MOSトランジスターの断面図である。
図9は本発明の第2実施例によるMOSトランジスターの断面図である。
図10は本発明の第3実施例によるMOSトランジスターの断面図として、高濃度ソース/ドレーン領域(40)をドープエピタキシャル層で形成したことを除いては、上述した第2実施例と同一である。
図11は本発明の第4実施例によるメモリセルトランジスターの断面図である。
12、52 ゲート絶縁膜
18、58 ゲート電極
20、60 ゲートキャッピング層
22、62 第1絶縁膜
24 犠牲スペーサ
25、75 ゲート構造物
26、66 第1絶縁膜
28、68 低濃度ソース/ドレーン領域
30 ソース/ドレーン拡張層
32、72 ゲートスペーサ
34、38、40、70a、70b 高濃度ソース/ドレーン領域
36 金属シリサイド層
Claims (14)
- 半導体基板と、
前記半導体基板上に順次で形成されたゲート絶縁膜及びゲート電極を含むゲート構造物と、
前記ゲート構造物の上面及び側面上に形成された第1絶縁膜と、
前記第1絶縁膜から離隔され前記半導体基板上に形成された第2絶縁膜と、
前記第2絶縁膜と前記ゲート構造物間の基板表面に形成された低濃度ソース/ドレーン領域と、
前記低濃度ソース/ドレーン領域上に第2絶縁膜とゲート構造物間の間隙を埋めて、前記第2絶縁膜上に延びられるように形成された高濃度ソース/ドレーン領域を備えて、
前記高濃度ソース/ドレーン領域のうちのいずれか一つ領域が隣接する二つの前記ゲート構造物間の第2絶縁膜上で連結されるように形成されたことを特徴とする半導体装置。 - 前記高濃度ソース/ドレーン領域はドープエピタキシャル層で形成されたことを特徴とする請求項1に記載の半導体装置。
- 半導体基板上にゲート絶縁膜及びゲート電極が順次に積層されたゲート構造物を形成する段階と、
前記ゲート構造物の上面、第1側面及び第2側面上に第1絶縁膜を形成する段階と、
前記基板上に前記第1絶縁膜から離隔されるように第2絶縁膜を形成する段階と、
前記第2絶縁膜と前記ゲート構造物間の基板表面に不純物をイオン注入して低濃度ソース/ドレーン領域を形成する段階と、
前記低濃度ソース/ドレーン領域上にソース/ドレーン拡張層を形成する段階と、
前記第2絶縁膜上にソース/ドレーン拡張層と連結されるように高濃度ソース/ドレーン領域を形成する段階とを備えることを特徴とする半導体装置の製造方法。 - 前記ソース/ドレーン拡張層は選択的エピタキシャル成長法によるドープエピタキシャルで形成することを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記高濃度ソース/ドレーン領域はドープポリシリコン層を蒸着して形成することを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記第2絶縁膜を形成する段階は、
前記第1絶縁膜の第1側面及び第2側面上に犠牲スペーサを形成する段階と、
酸化工程を実施して前記犠牲スペーサにより露出された基板上に第2絶縁膜を形成する段階と、
前記犠牲スペーサを除去する段階とを含むことを特徴とする請求項3に記載の半導体装置の製造方法。 - 前記犠牲スペーサはシリコン窒化物で形成することを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記高濃度ソース/ドレーン領域を形成する段階前に、前記ゲート構造物の両側壁に絶縁物質からなったゲートスペーサを形成する段階をさらに備えることを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記ゲートスペーサはシリコン窒化物で形成されることを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記ゲートスペーサは前記ソース/ドレーン拡張層と同一な幅で形成することを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記第1及び第2絶縁膜はシリコン酸化物で形成することを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記ゲート構造物は前記ゲート電極上に形成されたゲートキャッピング層をさらに備えることを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記ゲートキャッピング層はシリコン窒化物で形成することを特徴とする請求項12に記載の半導体装置の製造方法。
- 前記高濃度ソース/ドレーン領域を形成する段階後、前記高濃度ソース/ドレーン領域の表面に金属シリサイド層を形成する段階をさらに備えることを特徴とする請求項3に記載の半導体装置の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0065649A KR100485690B1 (ko) | 2002-10-26 | 2002-10-26 | 모스 트랜지스터 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004146825A JP2004146825A (ja) | 2004-05-20 |
JP4519442B2 true JP4519442B2 (ja) | 2010-08-04 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2003358405A Expired - Fee Related JP4519442B2 (ja) | 2002-10-26 | 2003-10-17 | Mosトランジスター及びその製造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US7119435B2 (ja) |
JP (1) | JP4519442B2 (ja) |
KR (1) | KR100485690B1 (ja) |
CN (1) | CN100435353C (ja) |
DE (1) | DE10341359B4 (ja) |
GB (1) | GB2395602B (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2005332993A (ja) * | 2004-05-20 | 2005-12-02 | Sanyo Electric Co Ltd | 半導体装置および半導体装置の製造方法 |
KR100613349B1 (ko) * | 2004-12-22 | 2006-08-21 | 동부일렉트로닉스 주식회사 | 두 개 이상의 구동 전압을 갖는 게이트를 포함하는 반도체소자 및 그 제조 방법 |
US7414277B1 (en) * | 2005-04-22 | 2008-08-19 | Spansion, Llc | Memory cell having combination raised source and drain and method of fabricating same |
JP2007027231A (ja) * | 2005-07-13 | 2007-02-01 | Seiko Epson Corp | 半導体装置の製造方法及び、半導体装置 |
KR100701405B1 (ko) * | 2005-11-21 | 2007-03-28 | 동부일렉트로닉스 주식회사 | 모스트랜지스터 및 그 제조방법 |
US7977185B2 (en) * | 2005-11-22 | 2011-07-12 | International Business Machines Corporation | Method and apparatus for post silicide spacer removal |
US11049939B2 (en) | 2015-08-03 | 2021-06-29 | Semiwise Limited | Reduced local threshold voltage variation MOSFET using multiple layers of epi for improved device operation |
US11373696B1 (en) | 2021-02-19 | 2022-06-28 | Nif/T, Llc | FFT-dram |
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-
2002
- 2002-10-26 KR KR10-2002-0065649A patent/KR100485690B1/ko active IP Right Grant
-
2003
- 2003-05-15 US US10/440,354 patent/US7119435B2/en not_active Expired - Lifetime
- 2003-05-26 CN CNB03136988XA patent/CN100435353C/zh not_active Expired - Lifetime
- 2003-09-08 DE DE10341359A patent/DE10341359B4/de not_active Expired - Lifetime
- 2003-09-18 GB GB0321893A patent/GB2395602B/en not_active Expired - Lifetime
- 2003-10-17 JP JP2003358405A patent/JP4519442B2/ja not_active Expired - Fee Related
-
2006
- 2006-05-03 US US11/381,517 patent/US20060211197A1/en not_active Abandoned
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JPH0318062A (ja) * | 1989-06-15 | 1991-01-25 | Toshiba Corp | 半導体装置 |
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JPH08340113A (ja) * | 1995-06-07 | 1996-12-24 | Sgs Thomson Microelectron Inc | 集積回路において平坦化構造を形成する方法 |
JPH10200106A (ja) * | 1997-01-13 | 1998-07-31 | Sony Corp | 半導体装置及びその製造方法 |
JP2000114262A (ja) * | 1998-10-05 | 2000-04-21 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2001223355A (ja) * | 2000-02-09 | 2001-08-17 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002280551A (ja) * | 2001-01-16 | 2002-09-27 | Chartered Semiconductor Mfg Ltd | 階段形状の絶縁層上に隆起した自己整合ソース/ドレーンcmosデバイスを製造する方法 |
Also Published As
Publication number | Publication date |
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JP2004146825A (ja) | 2004-05-20 |
DE10341359B4 (de) | 2007-12-27 |
CN100435353C (zh) | 2008-11-19 |
GB2395602A (en) | 2004-05-26 |
DE10341359A1 (de) | 2004-06-03 |
US20040080003A1 (en) | 2004-04-29 |
KR100485690B1 (ko) | 2005-04-27 |
GB0321893D0 (en) | 2003-10-22 |
CN1492515A (zh) | 2004-04-28 |
US20060211197A1 (en) | 2006-09-21 |
US7119435B2 (en) | 2006-10-10 |
GB2395602B (en) | 2005-03-02 |
KR20040036452A (ko) | 2004-04-30 |
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