JP4403462B2 - オンダイターミネーション回路を備えた半導体メモリ装置 - Google Patents
オンダイターミネーション回路を備えた半導体メモリ装置 Download PDFInfo
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- JP4403462B2 JP4403462B2 JP2005072388A JP2005072388A JP4403462B2 JP 4403462 B2 JP4403462 B2 JP 4403462B2 JP 2005072388 A JP2005072388 A JP 2005072388A JP 2005072388 A JP2005072388 A JP 2005072388A JP 4403462 B2 JP4403462 B2 JP 4403462B2
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- die termination
- data
- data input
- memory device
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/028—Arrangements specific to the transmitter end
- H04L25/0284—Arrangements to ensure DC-balance
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Logic Circuits (AREA)
- Memory System (AREA)
Description
60 入力バッファ
70 出力バッファ
SW1〜SW6 スイッチ
DQ、/DQ データ入出力パッド
Claims (6)
- データ入出力パッドと、
該データ入出力パッドから伝送されるデータをバッファリングして伝送するデータ入力バッファと、
メモリ装置が接続されたボードから伝送されるオンダイターミネーション電圧が印加されるオンダイターミネーションパッドと、
該オンダイターミネーションパッドと前記データ入出力パッドとの間に設けられたオンダイターミネーション抵抗と、
前記データ入力バッファにデータが入力される間、前記オンダイターミネーション抵抗と、前記オンダイターミネーションパッドとを接続するスイッチと、
前記スイッチを介して、前記オンダイターミネーション抵抗に接続された、オンダイターミネーション電圧を生成するオンダイターミネーション電圧発生部とを備え、
前記スイッチが、前記オンダイターミネーション電圧発生部で生成されたオンダイターミネーション電圧、または前記オンダイターミネーションパッドを介して伝送されたオンダイターミネーション電圧を前記データ入力バッファの入力ノードに提供するようにスイッチングされることを特徴とする半導体メモリ装置。 - 前記オンダイターミネーション抵抗が、抵抗値の制御が可能な可変抵抗器で構成されていることを特徴とする請求項1に記載の半導体メモリ装置。
- 前記データ入出力パッドを介して、データを外部に伝送するデータ出力バッファを、さらに備えることを特徴とする請求項1に記載の半導体メモリ装置。
- 第1データ入力ノードに接続され、データ信号を受信し、伝送する第1データ入出力パッドと、
第2データ入力ノードに接続され、反転された前記データ信号を受信して、伝送する第2データ入出パッドと、
オンダイターミネーション電圧を出力するオンダイターミネーション電圧発生部と、
一端側が前記第1データ入力ノードに接続された第1オンダイターミネーション抵抗と、
一端側が前記第2データ入力ノードに接続された第2オンダイターミネーション抵抗と、
前記第1オンダイターミネーション抵抗の他端側に接続される第1スイッチと、
前記第2オンダイターミネーション抵抗の他端側に接続される第2スイッチと、
前記第1データ入出力パッド及び前記第2データ入出力パッドから伝送されるデータ信号とその反転された信号とを比較して、メモリコアに伝送するデータ比較部とを備え、
前記第1スイッチ及び前記第2スイッチが、前記第1データ入力ノード及び前記第2データ入力ノードを介してデータが入力される間、前記オンダイターミネーション電圧発生部で生成されたオンダイターミネーション電圧を各々前記第1データ入力ノード及び前記第2データ入力ノードに提供するようにスイッチングされる
ことを特徴とする半導体メモリ装置。 - 前記第1及び第2オンダイターミネーション抵抗が、抵抗値の制御が可能な可変抵抗器で構成されていることを特徴とする請求項4に記載の半導体メモリ装置。
- 前記第1データ入出力パッドを介して、外部にデータ信号を伝送する第1データ出力バッファと、
前記第2データ入出力パッドを介して、外部に反転された前記データ信号を伝送する第2データ出力バッファとを、さらに備えることを特徴とする請求項4に記載の半導体メモリ装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040087725A KR100670702B1 (ko) | 2004-10-30 | 2004-10-30 | 온다이 터미네이션 회로를 구비한 반도체 메모리 장치 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006129423A JP2006129423A (ja) | 2006-05-18 |
JP4403462B2 true JP4403462B2 (ja) | 2010-01-27 |
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JP2005072388A Expired - Fee Related JP4403462B2 (ja) | 2004-10-30 | 2005-03-15 | オンダイターミネーション回路を備えた半導体メモリ装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7161378B2 (ja) |
JP (1) | JP4403462B2 (ja) |
KR (1) | KR100670702B1 (ja) |
CN (1) | CN100508067C (ja) |
TW (1) | TWI303436B (ja) |
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US6980020B2 (en) * | 2003-12-19 | 2005-12-27 | Rambus Inc. | Calibration methods and circuits for optimized on-die termination |
US7173450B2 (en) * | 2004-06-01 | 2007-02-06 | Hewlett-Packard Development Company, L.P. | Bus controller |
-
2004
- 2004-10-30 KR KR1020040087725A patent/KR100670702B1/ko not_active IP Right Cessation
- 2004-12-30 TW TW093141293A patent/TWI303436B/zh not_active IP Right Cessation
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2005
- 2005-01-05 US US11/030,558 patent/US7161378B2/en not_active Expired - Fee Related
- 2005-03-15 JP JP2005072388A patent/JP4403462B2/ja not_active Expired - Fee Related
- 2005-05-18 CN CNB2005100706966A patent/CN100508067C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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CN100508067C (zh) | 2009-07-01 |
JP2006129423A (ja) | 2006-05-18 |
TWI303436B (en) | 2008-11-21 |
KR20060038629A (ko) | 2006-05-04 |
US20060091900A1 (en) | 2006-05-04 |
KR100670702B1 (ko) | 2007-01-17 |
US7161378B2 (en) | 2007-01-09 |
CN1770323A (zh) | 2006-05-10 |
TW200614255A (en) | 2006-05-01 |
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