JP2020526952A - パッケージ光活性ガラス基板内のrfシステムのための2d及び3dのrf集中素子デバイス - Google Patents
パッケージ光活性ガラス基板内のrfシステムのための2d及び3dのrf集中素子デバイス Download PDFInfo
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- JP2020526952A JP2020526952A JP2019570136A JP2019570136A JP2020526952A JP 2020526952 A JP2020526952 A JP 2020526952A JP 2019570136 A JP2019570136 A JP 2019570136A JP 2019570136 A JP2019570136 A JP 2019570136A JP 2020526952 A JP2020526952 A JP 2020526952A
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Classifications
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- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- C03C15/00—Surface treatment of glass, not in the form of fibres or filaments, by etching
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- C03C23/00—Other surface treatment of glass not in the form of fibres or filaments
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- C03—GLASS; MINERAL OR SLAG WOOL
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- C03C23/00—Other surface treatment of glass not in the form of fibres or filaments
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- C03C3/00—Glass compositions
- C03C3/04—Glass compositions containing silica
- C03C3/076—Glass compositions containing silica with 40% to 90% silica, by weight
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- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C4/00—Compositions for glass with special properties
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- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
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- H01P11/00—Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
- H01P11/001—Manufacturing waveguides or transmission lines of the waveguide type
- H01P11/003—Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines
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- H03H7/01—Frequency selective two-port networks
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- H03H7/1741—Comprising typical LC combinations, irrespective of presence and location of additional resistors
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
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- C03C2217/251—Al, Cu, Mg or noble metals
- C03C2217/253—Cu
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- H—ELECTRICITY
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- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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Abstract
Description
なし
なし
Ce3+ + Ag+ = Ce4+ + Ag0
である。
Claims (29)
- 集積化集中素子デバイスが光限定性ガラスの中又は上にシステムインパッケージ(SiP,system-in-package)として形成された、パッケージ内のシステムを生成するための方法であって、
1又は2以上の構造体を備える設計レイアウトをマスキングして、感光性ガラス基板の上又は中に1又は2以上の電気的構成要素を形成するステップと、
前記感光性ガラス基板の少なくとも一部分を活性化エネルギー源に露光するステップと、
少なくとも10分間、前記感光性ガラス基板をそのガラス転移温度を超えて加熱するステップと、
前記露光されたガラスの少なくとも一部を結晶材料に変換させるように前記感光性ガラス基板を冷却して、ガラス結晶基板を形成するステップと、
前記ガラス結晶基板をエッチャント溶液でエッチングして、前記デバイス内に1又は2以上のチャネルを形成するステップであって、前記ガラス結晶基板が、トレンチに隣接しており、セラミック相に変換されてもよい、ステップと、
前記トレンチを充填し前記光限定性ガラスの表面上に堆積する銅の電気めっきを可能にするように、前記エッチングステップ中に露光される前記ガラス結晶基板の表面においてシード層を堆積、成長、又は選択的にエッチングして生成するステップとを含み、
前記集積化集中素子デバイスが、等価な表面実装型デバイスと比較したとき、光限定性ガラスの中又は上にシステムインパッケージ(SiP)に実装されるパッケージ集中素子デバイスから寄生雑音及び損失を少なくとも25%、低減させる、
前記方法。 - 集積化集中素子デバイスがSiP内にあるアイソレータを形成するステップをさらに含む、請求項1に記載の方法。
- 集積化集中素子デバイスがSiP内にあるサーキュレータを形成するステップをさらに含む、請求項1に記載の方法。
- 集積化集中素子デバイスがSiP内にあるRFフィルタを形成するステップをさらに含む、請求項1に記載の方法。
- 集積化集中素子デバイスがSiP内にあるローパス、ハイパスフィルタ、ノッチフィルタ、バンドパスフィルタ、変成器、サーキュレータ、アイソレータのうちの少なくとも1つを形成するステップをさらに含む、請求項1に記載の方法。
- 光限定性ガラス基板の中又は上に電力結合器、電力分割器RF回路を形成するステップをさらに含む、請求項1に記載の方法。
- 基板への実装素子のパッケージ化に関連するRF寄生信号の少なくとも30%を排除するSiP RF回路を形成するステップをさらに含む、請求項1に記載の方法。
- 基板への実装素子のパッケージ化に関連するRF寄生信号の少なくとも35%を排除するSiP RF回路を形成するステップをさらに含む、請求項1に記載の方法。
- 1又は2以上のRFフィルタ、RFサーキュレータ、RFアイソレータ、アンテナ、インピーダンスマッチング素子、50オーム終端素子、集積化接地板、RF遮蔽素子、EMI遮蔽素子、RF結合器、RF分割器、変成器、スイッチ、電力分割器、電力結合器、及び/又はダイプレクサを形成するステップをさらに含む、請求項1に記載の方法。
- 請求項1に記載の方法によって作製される光限定性ガラスの中又は上のシステムインパッケージ(SiP,system-in-package)に実装されるパッケージ集中素子デバイス。
- 集積化集中素子デバイスがSiP内にあるアイソレータである、請求項10に記載のデバイス。
- 集積化集中素子デバイスがSiP内にあるサーキュレータである、請求項10に記載のデバイス。
- 集積化集中素子デバイスがSiP内にあるRFフィルタである、請求項10に記載のデバイス。
- 集積化集中素子デバイスがSiP内にあるローパス、ハイパスフィルタ、ノッチフィルタ、バンドパスフィルタ、変成器、サーキュレータ、アイソレータのうちの少なくとも1つである、請求項10に記載のデバイス。
- 光限定性ガラス基板の中又は上の電力結合器、電力分割器RF回路である、請求項10に記載のデバイス。
- 等価な表面実装型デバイスと比較したとき、RF寄生信号損失の少なくとも30%を排除するSiP RF回路である、請求項10に記載のデバイス。
- 等価な表面実装型デバイスと比較したとき、RF寄生信号損失の少なくとも35%を排除するSiP RF回路である、請求項10に記載のデバイス。
- 等価な表面実装型デバイスと比較したとき、RF寄生信号損失の少なくとも50%を排除するSiP RF回路を形成するステップをさらに含む、請求項10に記載のデバイス。
- 1又は2以上のRFフィルタ、RFサーキュレータ、RFアイソレータ、アンテナ、インピーダンスマッチング素子、50オーム終端素子、集積化接地板、RF遮蔽素子、EMI遮蔽素子、RF結合器、RF分割器、変成器、スイッチ、電力分割器、電力結合器、及び/又はダイプレクサである、請求項10に記載のデバイス。
- 集積化集中素子デバイスが光限定性ガラスの中又は上にシステムインパッケージ(SiP,system-in-package)として形成された、パッケージ内のシステムを生成するための方法であって、
1又は2以上の構造体を備える設計レイアウトをマスキングして、感光性ガラス基板の上又は中に1又は2以上の電気的構成要素を形成するステップと、
前記露光されたガラスの少なくとも一部を結晶材料に変換して、ガラス結晶基板を形成するステップと、
前記ガラス結晶基板をエッチャント溶液でエッチングして、前記デバイス内に1又は2以上のチャネルを形成するステップであって、前記ガラス結晶基板が、トレンチに隣接しており、セラミック相に変換されてもよい、ステップと、
前記トレンチを充填し前記光限定性ガラスの表面上に堆積する銅の電気めっきを可能にするように、前記エッチングステップ中に露光される前記ガラス結晶基板の表面においてシード層を堆積、成長、又は選択的にエッチングするステップとを含み、
前記集積化集中素子デバイスが、等価な表面実装型デバイスと比較したとき、光限定性ガラスの中又は上にシステムインパッケージ(SiP)に実装されるパッケージ集中素子デバイスから寄生雑音及び損失を少なくとも25%、低減させる、
前記方法。 - 集積化集中素子デバイスがSiP内にあるアイソレータを形成するステップをさらに含む、請求項20に記載の方法。
- 集積化集中素子デバイスがSiP内にあるサーキュレータを形成するステップをさらに含む、請求項20に記載の方法。
- 集積化集中素子デバイスがSiP内にあるRFフィルタを形成するステップをさらに含む、請求項20に記載の方法。
- 集積化集中素子デバイスがSiP内にあるローパス、ハイパスフィルタ、ノッチフィルタ、バンドパスフィルタ、変成器、サーキュレータ、アイソレータのうちの少なくとも1つを形成するステップをさらに含む、請求項20に記載の方法。
- 光限定性ガラス基板の中又は上に電力結合器、電力分割器RF回路を形成するステップをさらに含む、請求項20に記載の方法。
- 基板への実装素子のパッケージ化に関連するRF寄生信号の少なくとも30%を排除するSiP RF回路を形成するステップをさらに含む、請求項20に記載の方法。
- 基板への実装素子のパッケージ化に関連するRF寄生信号の少なくとも35%を排除するSiP RF回路を形成するステップをさらに含む、請求項20に記載の方法。
- 等価な表面実装型デバイスと比較したとき、RF寄生信号損失の少なくとも50%を排除するSiP RF回路を形成するステップをさらに含む、請求項20に記載の方法。
- 1又は2以上のRFフィルタ、RFサーキュレータ、RFアイソレータ、アンテナ、インピーダンスマッチング素子、50オーム終端素子、集積化接地板、RF遮蔽素子、EMI遮蔽素子、RF結合器、RF分割器、変成器、スイッチ、電力分割器、電力結合器、及び/又はダイプレクサを形成するステップをさらに含む、請求項20に記載の方法。
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KR102386799B1 (ko) | 2022-04-18 |
KR20200026926A (ko) | 2020-03-11 |
AU2021201253A1 (en) | 2021-03-18 |
US20200212864A1 (en) | 2020-07-02 |
CA3067812A1 (en) | 2019-01-10 |
AU2018297035A1 (en) | 2020-01-23 |
US11342896B2 (en) | 2022-05-24 |
EP3649733A1 (en) | 2020-05-13 |
AU2018297035B2 (en) | 2021-02-25 |
CA3067812C (en) | 2023-03-14 |
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JP6995891B2 (ja) | 2022-01-17 |
WO2019010045A1 (en) | 2019-01-10 |
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KR102418671B1 (ko) | 2022-07-12 |
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