JP2014209727A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2014209727A JP2014209727A JP2014057698A JP2014057698A JP2014209727A JP 2014209727 A JP2014209727 A JP 2014209727A JP 2014057698 A JP2014057698 A JP 2014057698A JP 2014057698 A JP2014057698 A JP 2014057698A JP 2014209727 A JP2014209727 A JP 2014209727A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/24—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using capacitors
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
Abstract
【解決手段】シュミットトリガ型NAND回路及びシュミットトリガ型インバータを有し、電源電圧の供給が継続する期間においてデータが保持され、電源電圧の供給が停止された期間より前に、容量素子が電気的に接続されたノードにデータに対応する電位を退避させる。そして、該ノードにゲートが接続されたトランジスタのチャネル抵抗が変化することを利用して、電源電圧の供給の再開に応じて、データの復元を行う構成とする。
【選択図】図1
Description
本実施の形態では、不揮発性部及び揮発性部を有する半導体装置の一例について説明する。
本実施の形態では、不揮発性部及び揮発性部を有する半導体装置の一例について説明する。
本実施の形態では、不揮発性部及び揮発性部を有する半導体装置の一例について説明する。
本実施の形態では、半導体装置の応用例について具体例を挙げて説明する。
本実施の形態では、トランジスタのチャネルに適用できる酸化物半導体について説明する。
本実施の形態では、半導体装置の一例について説明する。図15に、図1、図5及び図7に示した半導体装置が有する、トランジスタ610、トランジスタ611の断面構造を、一例として示す。
本発明の一態様に係る半導体装置は、表示機器、パーソナルコンピュータ、記録媒体を備えた画像再生装置(代表的にはDVD:Digital Versatile Disc等の記録媒体を再生し、その画像を表示しうるディスプレイを有する装置)に用いることができる。その他に、本発明の一態様に係る半導体装置を用いることができる電子機器として、携帯電話、携帯型を含むゲーム機、携帯情報端末、電子書籍、ビデオカメラ、デジタルスチルカメラ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、ナビゲーションシステム、音響再生装置(カーオーディオ、デジタルオーディオプレイヤー等)、複写機、ファクシミリ、プリンター、プリンター複合機、現金自動預け入れ払い機(ATM)、自動販売機などが挙げられる。これら電子機器の具体例を図17に示す。
101 ゲート部
102 ラッチ部
110 ST−NAND
111 ST−NAND
112 ST−NAND
113 ST−NAND
116 ノード
117 ノード
150 第2の記憶回路部
151 第1のブロック
152 第2のブロック
160 ST−INV
161 トランジスタ
162 トランジスタ
163 トランジスタ
164 容量素子
165 ノード
170 ST−INV
171 トランジスタ
172 トランジスタ
173 トランジスタ
174 容量素子
175 ノード
200 配線
201 配線
202 配線
203 ST−NAND
210 トランジスタ
211 トランジスタ
212 トランジスタ
213 トランジスタ
214 トランジスタ
215 トランジスタ
216 トランジスタ
217 トランジスタ
218 トランジスタ
219 トランジスタ
250 配線
251 配線
252 配線
253 ST−AND
300 配線
301 配線
302 ST−INV
310 トランジスタ
311 トランジスタ
312 トランジスタ
313 トランジスタ
314 トランジスタ
315 トランジスタ
400 第1の記憶回路部
401 ゲート部
402 ラッチ部
410 ST−NAND
411 ST−NAND
412 ST−NAND
413 ST−AND
414 ST−NAND
415 ST−NAND
416 ST−NAND
421 ノード
423 ノード
424 ノード
426 ノード
427 ノード
450 第2の記憶回路部
451 第1のブロック
452 第2のブロック
460 ST−INV
461 トランジスタ
462 トランジスタ
463 トランジスタ
464 容量素子
465 ノード
470 ST−INV
471 トランジスタ
472 トランジスタ
473 トランジスタ
474 容量素子
475 ノード
500 第1の記憶回路部
501 ゲート部
502 マスタ・ラッチ
503 ゲート部
504 スレーブ・ラッチ
510 ST−NAND
511 ST−NAND
512 ST−NAND
513 ST−NAND
516 ノード
517 ノード
530 ST−NAND
531 ST−NAND
532 ST−NAND
533 ST−NAND
536 ノード
537 ノード
550 第2の記憶回路部
551 第1のブロック
552 第2のブロック
553 第3のブロック
554 第4のブロック
560 ST−INV
561 トランジスタ
562 トランジスタ
563 トランジスタ
564 容量素子
565 ノード
570 ST−INV
571 トランジスタ
572 トランジスタ
573 トランジスタ
574 容量素子
575 ノード
580 ST−INV
581 トランジスタ
582 トランジスタ
583 トランジスタ
584 容量素子
585 ノード
590 ST−INV
591 トランジスタ
592 トランジスタ
593 トランジスタ
594 容量素子
595 ノード
610 トランジスタ
611 トランジスタ
700 ロジックアレイ
701 LE
702 スイッチ部
703 配線群
704 配線群
705 入出力端子
711 LUT
712 フリップフロップ
713 マルチプレクサ
714 コンフィギュレーションメモリ
715 コンフィギュレーションメモリ
716 入力端子
717 出力端子
820 絶縁膜
830 半導体膜
830a 酸化物半導体層
830b 酸化物半導体層
830c 酸化物半導体層
831 ゲート絶縁膜
832 導電膜
833 導電膜
834 ゲート電極
900 コンフィギュレーションメモリ
901 データ線
902 ワード線
903 ワード線
911 トランジスタ
912 トランジスタ
913 トランジスタ
914 容量素子
920 コンフィギュレーションメモリ
931 トランジスタ
932 トランジスタ
933 トランジスタ
934 容量素子
935 トランジスタ
936 トランジスタ
937 トランジスタ
938 容量素子
940 インバータ回路
941 データ線
942 ワード線
943 ワード線
1000 CPU
1001 主記憶装置
1011 プログラムカウンタ
1012 命令レジスタ
1013 命令デコーダ
1014 汎用レジスタ
1015 ALU
1021 パワースイッチ
1022 電源制御回路
1110A トランジスタ
1400 半導体基板
1401 素子分離用絶縁膜
1402 不純物領域
1403 不純物領域
1404 ゲート電極
1405 ゲート絶縁膜
1409 絶縁膜
1410 配線
1411 配線
1412 配線
1415 配線
1416 配線
1417 配線
1420 絶縁膜
1421 配線
1430 半導体膜
1431 ゲート絶縁膜
1432 導電膜
1433 導電膜
1434 ゲート電極
1440 絶縁膜
1441 絶縁膜
1442 絶縁膜
1443 導電膜
5001 筐体
5002 筐体
5003 表示部
5004 表示部
5005 マイクロホン
5006 スピーカ
5007 操作キー
5008 スタイラス
5101 車体
5102 車輪
5103 ダッシュボード
5104 ライト
5301 筐体
5302 冷蔵室用扉
5303 冷凍室用扉
5401 筐体
5402 表示部
5403 キーボード
5404 ポインティングデバイス
5601 筐体
5602 筐体
5603 表示部
5604 表示部
5605 接続部
5606 操作キー
5801 筐体
5802 筐体
5803 表示部
5804 操作キー
5805 レンズ
5806 接続部
Claims (6)
- 第1の記憶回路部と、第2の記憶回路部とを有し、
前記第1の記憶回路部は、第1の電位または第2の電位の一方を保持する第1のノードと、第1の電位または第2の電位の他方を保持する第2のノードと、を有し、
前記第2の記憶回路部は、第1及び第2のインバータと、第1及び第2のトランジスタと、第1乃至第4のスイッチと、第1及び第2の容量素子と、第3及び第4のノードを有し、
前記第1のインバータの入力端子は、前記第1のノードに電気的に接続され、
前記第1のインバータの出力端子は、前記第1のスイッチを介して、前記第3のノードと電気的に接続され、
前記第3のノードは、前記第1のトランジスタのゲート及び前記第1の容量素子の第1の電極と電気的に接続され、
前記第1の容量素子の第2の電極及び前記第1のトランジスタのソースまたはドレインの一方は、第1の電位が与えられる配線に電気的に接続され、
前記第1のトランジスタのソースまたはドレインの他方は、前記第2のスイッチを介して、前記第1のノードと電気的に接続され、
前記第2のインバータの入力端子は、前記第2のノードに電気的に接続され、
前記第2のインバータの出力端子は、前記第3のスイッチを介して、前記第4のノードと電気的に接続され、
前記第4のノードは、前記第2のトランジスタのゲート及び前記第2の容量素子の第1の電極と電気的に接続され、
前記第2の容量素子の第2の電極及び前記第2のトランジスタのソースまたはドレインの一方は、第1の電位が与えられる配線に電気的に接続され、
前記第2のトランジスタのソースまたはドレインの他方は、前記第4のスイッチを介して、前記第2のノードと電気的に接続される、ことを特徴とする半導体装置。 - 請求項1において、
前記第1の記憶回路部は、電源電圧の供給が継続されている期間において、前記第1のノードに、前記第1の電位または前記第2の電位の一方を保持し、前記第2のノードに、前記第1の電位または前記第2の電位の他方を保持し、
前記第2の記憶回路部は、電源電圧の供給が停止する期間において、前記第3のノードに、前記第1の電位または前記第2の電位の他方を保持し、前記第4のノードに、前記第1の電位または前記第2の電位の一方を保持することを特徴とする半導体装置。 - 請求項1乃至請求項2のいずれか1項において、前記第1乃至第4のスイッチは、トランジスタを有することを特徴とする半導体装置。
- 請求項1乃至請求項3のいずれか1項において、前記第1乃び第3のスイッチは、酸化物半導体膜にチャネル形成領域を有するトランジスタであることを特徴とする半導体装置。
- 請求項1乃至請求項4のいずれか1項において、前記第1の記憶回路部は、シュミットトリガ型NAND回路を有することを特徴とする半導体装置。
- 請求項1乃至請求項5のいずれか1項において、前記第1及び第2のインバータは、シュミットトリガ型インバータを有することを特徴とする半導体装置。
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JP6445243B2 (ja) | 2018-12-26 |
US20140286076A1 (en) | 2014-09-25 |
JP2019047519A (ja) | 2019-03-22 |
TWI618079B (zh) | 2018-03-11 |
WO2014157019A1 (en) | 2014-10-02 |
TW201501130A (zh) | 2015-01-01 |
US9245589B2 (en) | 2016-01-26 |
JP6890572B2 (ja) | 2021-06-18 |
JP2016122839A (ja) | 2016-07-07 |
JP6074488B2 (ja) | 2017-02-01 |
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