JP2013521651A - 浮遊ボディセル、浮遊ボディセルを含むデバイス、ならびに浮遊ボディセルの形成方法。 - Google Patents
浮遊ボディセル、浮遊ボディセルを含むデバイス、ならびに浮遊ボディセルの形成方法。 Download PDFInfo
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/056—Making the transistor the transistor being a FinFET
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
Abstract
Description
幾つかの実施形態においては、本発明は、浮遊ボディセル構造、浮遊ボディセル構造を含むデバイスおよび浮遊ボディセル構造を形成するための方法を含む。浮遊ボディセル構造は、バックゲート、少なくとも一つの浮遊ボディ、少なくとも一つの浮遊ボディに関連付けられる別のゲートを含みうる。少なくとも一つの浮遊ボディは、半導電性材料を含み、バックゲートから、ソース領域およびドレイン領域へと伸長しうる。ソース領域およびドレイン領域は、少なくとも一つの浮遊ボディによって、バックゲートから間隔を開けられうる。少なくとも一つの浮遊ボディは、半導電性材料における間隙を含み、ソース領域およびドレイン領域の各々は、逆のバックゲートに配置される。別のゲートは、少なくとも一つの浮遊ボディにおける間隙内に配置されて、ダブルゲート浮遊ボディセル構造を形成するか、または、少なくとも一つの浮遊ボディの少なくとも一つの表面上に配置されて、トリプルゲート浮遊ボディセル構造を形成する。ゲート誘電体は、バックゲート、少なくとも一つの浮遊ボディ、およびバックゲートの下層にあり、ウェーハ上に配置された非晶質シリコン材料の間に配置されうる。バックゲートは、少なくとも一つの浮遊ボディの側壁に沿って配列された連続的な側壁を含むローカルバックゲートであるか、または、複数の浮遊ボディセルがアレイ内に配置されたグローバルバックゲートでありうる。浮遊ボディセル構造は、バックゲートに電気的に結合され、バックゲートを独立してバイアスするためのバイアス電圧に任意で結合されるビット線をさらに含んでもよい。浮遊ボディセル構造は、少なくとも一つの浮遊ボディセルのソース領域を、少なくとも別の浮遊ボディのソース領域へと電気的に結合する共通のソース線と、少なくとも一つの浮遊ボディセルのドレイン領域を、少なくとも別の浮遊ボディのドレイン領域へと電気的に結合するビット線と、をさらに含んでもよい。
本出願は、同一日に出願された同時係属中の米国特許出願整理番号12/XXX,XXX、”SEMICONDUCTOR-METAL-ON-INSULATOR STRUCTURES, METHODS OF FORMING SUCH STRUCTURES, AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES”(代理人整理番号2269-9742US)、同一日に出願された同時係属中の米国特許出願整理番号12/XXX,XXX、”SEMICONDUCTOR DEVICES INCLUDING A DIODE STRUCTURE OVER A CONDUCTIVE STRAP, AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES” (代理人整理番号2269-9803US)、同一日に出願された同時係属中の米国特許出願整理番号12/XXX,XXX、”THYRISTOR-BASED MEMORY CELLS, DEVICES AND SYSTEMS INCLUDING THE SAME AND METHODS FOR FORMING THE SAME” (代理人整理番号2269-9804US)、同一日に出願された同時係属中の米国特許出願整理番号12/XXX,XXX、”SEMICONDUCTOR CELLS, ARRAYS DEVICES AND SYSTEMS HAVING A BURIED CONDUCTIVE LINE AND METHODS FOR FORMING THE SAME” (代理人整理番号2269-9819US)に関連し、各々の開示は、参照によってその全体が本明細書に組み込まれる。
本出願は、2010年3月2日に出願された同時係属中の米国特許出願整理番号12/715,704、”SEMICONDUCTOR-METAL-ON-INSULATOR STRUCTURES, METHODS OF FORMING SUCH STRUCTURES, AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES”、2010年3月2日に出願された同時係属中の米国特許出願整理番号12/715,743、”SEMICONDUCTOR DEVICES INCLUDING A DIODE STRUCTURE OVER A CONDUCTIVE STRAP, AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES”、 2010年3月2日に出願された同時係属中の米国特許出願整理番号12/715,889、”THYRISTOR-BASED MEMORY CELLS, DEVICES AND SYSTEMS INCLUDING THE SAME AND METHODS FOR FORMING THE SAME”、2010年3月2日に出願された同時係属中の米国特許出願整理番号12/715,922、”SEMICONDUCTOR CELLS, ARRAYS DEVICES AND SYSTEMS HAVING A BURIED CONDUCTIVE LINE AND METHODS FOR FORMING THE SAME”に関連し、それらの開示は、参照によって本明細書に組み込まれる。
Claims (30)
- 浮遊ボディセル構造であって、
バックゲートと、
半導電性材料を含み、前記バックゲートからソース領域およびドレイン領域へと伸長する、少なくとも一つの浮遊ボディと、
前記少なくとも一つの浮遊ボディに関連付けられる別のゲートと、
を含む、
ことを特徴とする浮遊ボディセル構造。 - 前記ソース領域および前記ドレイン領域は、前記少なくとも一つの浮遊ボディによって、前記バックゲートから間隔が空いている、
ことを特徴とする請求項1に記載の浮遊ボディセル構造。 - 前記少なくとも一つの浮遊ボディは、前記半導電性材料内に間隙を含み、前記ソース領域および前記ドレイン領域の各々は、前記バックゲートとは逆に配置される、
ことを特徴とする請求項1に記載の浮遊ボディセル構造。 - 前記別のゲートは、前記少なくとも一つの浮遊ボディにおける前記間隙内に配置される、
ことを特徴とする請求項3に記載の浮遊ボディセル構造。 - 前記別のゲートは、トリプルゲート浮遊ボディセル構造を形成するために、前記少なくとも一つの浮遊ボディの少なくとも一つの表面上に配置される、
ことを特徴とする請求項1に記載の浮遊ボディセル構造。 - 前記バックゲートは、連続的で、かつ、前記少なくとも一つの浮遊ボディの複数の側壁に沿って配列される複数の側壁を含むローカルバックゲートを含む、
ことを特徴とする請求項1に記載の浮遊ボディセル構造。 - 前記少なくとも一つの浮遊ボディは、アレイ内の単一のバックゲート上に配置される複数の浮遊ボディを含む、
ことを特徴とする請求項1に記載の浮遊ボディセル構造。 - 前記バックゲートを独立してバイアスするためのバイアス電圧に対して、動作可能なように結合されるビット線をさらに含む、
ことを特徴とする請求項1に記載の浮遊ボディセル構造。 - 前記少なくとも一つの浮遊ボディセルの前記ソース領域を、少なくとも別の浮遊ボディのソース領域へと電気的に結合する共通のソース線と、前記少なくとも一つの浮遊ボディセルの前記ドレイン領域を、前記少なくとも別の浮遊ボディのドレイン領域へと電気的に結合するビット線と、をさらに含む、
ことを特徴とする請求項1に記載の浮遊ボディセル構造。 - バックゲートと、
各々が半導電性材料を含み、前記バックゲートからソース領域およびドレイン領域へと伸長する、複数の浮遊ボディと、
前記複数の浮遊ボディに関連付けられ、電圧源に動作可能なように結合される別のゲートと、
前記複数の浮遊ボディの前記複数のソース領域を電気的に結合する共通のソース線と、前記複数の浮遊ボディの前記複数のドレイン領域を電気的に結合するビット線と、
を含む、
ことを特徴とする浮遊ボディセルデバイス。 - ダイナミックランダムアクセスメモリ、ゼロキャパシタランダムアクセスメモリ、および、そこに統合された埋め込みダイナミックランダムアクセスメモリのうちの少なくとも一つをさらに含む、
ことを特徴とする請求項10に記載の浮遊ボディセルデバイス。 - 前記複数の浮遊ボディは、複数の行を形成するための第一の方向と、複数の列を形成するための、前記第一の方向とは実質的に直行する第二の方向とに配列される、
ことを特徴とする請求項10に記載の浮遊ボディセルデバイス。 - 複数の行を形成するために第一の方向に配列され、かつ、複数の列を形成するために、前記第一の方向とは実質的に直行する第二の方向に配列された複数の浮遊ボディを含み、各浮遊ボディは、
そのベース部分から伸長し、u形状トレンチによって分離される複数のピラーを有し、前記複数のピラーの各々の上部はドープ領域を含む、大量の半導電性材料と、
前記複数の浮遊ボディと関連付けられる少なくとも一つのバックゲートと、
前記複数の浮遊ボディに関連し、動作可能なように電圧源に結合される少なくとも別のゲートと、
を含む、
ことを特徴とする浮遊ボディセルデバイス - 前記少なくとも一つのバックゲートは、電気的に絶縁性の材料上の非晶質シリコン材料上に配置される、導電性材料を含む、
ことを特徴とする請求項13に記載の浮遊ボディセルデバイス。 - 前記少なくとも別のゲートは、前記複数の浮遊ボディの各々の上に配置される導電性材料を含む、
ことを特徴とする請求項13に記載の浮遊ボディセルデバイス。 - 前記導電性材料は、前記第一の方向に伸長し、前記複数の行のうちの少なくとも一つにおける前記複数の浮遊ボディを電気的に結合する、
ことを特徴とする請求項15に記載の浮遊ボディセルデバイス。 - 前記少なくとも別のゲートは、前記u形状トレンチ内に配置された導電性材料を含む、
ことを特徴とする請求項13に記載の浮遊ボディセルデバイス。 - 前記導電性材料は前記第二の方向に伸長し、前記複数の列のうちの少なくとも一つにおける前記複数の浮遊ボディを電気的に結合する、
ことを特徴とする請求項17に記載の浮遊ボディセルデバイス。 - 前記少なくとも一つのバックゲートは、前記少なくとも別のゲートからは独立してバイアスされるように構成される、
ことを特徴とする請求項13に記載の浮遊ボディセルデバイス。 - 前記浮遊ボディセル構造は、少なくとも一つの他の論理デバイスと垂直に積層される、
ことを特徴とする請求項13に記載の浮遊ボディセルデバイス。 - 浮遊ボディセルデバイスを形成する方法であって、
半導電性材料、誘電体材料、ゲート材料およびウェーハを被覆する非晶質シリコン材料を含むベースを形成するステップと、
前記ベースの表面から突出する複数の浮遊ボディを形成するために、前記半導電性材料の一部を除去するステップと、
前記複数の浮遊ボディにおける間隙を形成するために、前記半導電性材料の別の部分を除去するステップと、
前記複数の浮遊ボディの各々の複数の上部領域に、ソース領域およびドレイン領域を形成するために、前記複数の浮遊ボディを少なくとも一つのドーパントに暴露するステップと、
前記複数の浮遊ボディのうちの少なくとも一つに関連付けられるゲートを形成するステップと、
を含む、
ことを特徴とする方法。 - 半導電性材料、誘電体材料、ゲート材料および基板を被覆する非晶質シリコン材料を含むベースを形成するステップは、
誘電体材料、ゲート材料、および結晶質シリコンウェーハを被覆する非晶質シリコン材料を含むドナーウェーハを形成するステップと、
前記結晶質シリコンウェーハの所望の深度に複数のイオンを注入するステップと、
ハンドルウェーハを被覆する電気的に絶縁性の材料へと、前記ドナーウェーハの前記非晶質シリコン材料を接着するステップと、
前記結晶質シリコンウェーハ、前記誘電体材料、前記ゲート材料および、前記ハンドルウェーハの前記電気的に絶縁性の材料の表面を被覆する前記非晶質シリコン材料の一部を残すために、前記ドナーウェーハの一部を分離するステップと、
を含む、
ことを特徴とする請求項21に記載の方法。 - 前記ベースの表面から突出する前記複数の浮遊ボディを形成するために、前記半導電性材料の一部を除去するステップは、前記複数の浮遊ボディを形成するために、前記誘電体材料、前記ゲート材料および前記非晶質シリコン材料の一部を除去するステップをさらに含み、各浮遊ボディは、前記ウェーハを被覆する電気的に絶縁性の材料上に配置される、
ことを特徴とする請求項21に記載の方法。 - 前記複数の浮遊ボディのうちの少なくとも一つに関連付けられるゲートを形成するステップは、前記複数の浮遊ボディの各々の前記間隙内に導電性材料を堆積するステップを含む、
ことを特徴とする請求項21に記載の方法。 - 前記複数の浮遊ボディのうちの少なくとも一つに関連付けられるゲートを形成するステップは、前記複数の浮遊ボディの各々のうちの少なくとも一つの表面上に導電性構造を形成するステップを含む、
ことを特徴とする請求項21に記載の方法。 - 少なくとも一つのメモリデバイスと、
前記少なくとも一つのメモリデバイスに動作可能なように結合される、少なくとも一つの浮遊ボディセルデバイスであって、
アレイの各浮遊ボディは、そのベース部分から伸長し、u形状トレンチによって分離される複数のピラーを有する大量の半導電性材料を含み、前記複数のピラーの各々の上部は、ドープ領域を含む、複数の浮遊ボディのアレイと、
複数の浮遊ボディの前記アレイに関連付けられる少なくとも一つのバックゲートと、
複数の浮遊ボディの前記アレイに関連付けられ、動作可能なように電圧源に結合される少なくとも別のゲートと、
を含む、少なくとも一つの浮遊ボディデバイスと、
を含む、
ことを特徴とするシステム。 - 前記システムは、中央処理装置およびシステムオンチップのうちの少なくとも一つを含む、
ことを特徴とする請求項26に記載のシステム。 - 前記少なくとも一つのメモリデバイスは、ダイナミックランダムアクセスメモリ、ゼロキャパシタランダムアクセスメモリ、および埋め込みダイナミックランダムアクセスメモリのうちの少なくとも一つを含む、
ことを特徴とする請求項26に記載のシステム。 - 前記少なくとも一つのメモリデバイスおよび前記少なくとも一つの浮遊ボディセルデバイスは、お互いに重ねられる、
ことを特徴とする請求項26に記載のシステム。 - 複数の浮遊ボディの前記アレイは、第一の方向に配列され、かつ、前記第一の方向と実質的に直行する第二の方向に配列された複数の浮遊ボディを含む、
ことを特徴とする請求項26に記載のシステム。
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KR101471734B1 (ko) | 2014-12-10 |
CN102822972A (zh) | 2012-12-12 |
US8841715B2 (en) | 2014-09-23 |
KR20120123588A (ko) | 2012-11-08 |
US8530295B2 (en) | 2013-09-10 |
US8513722B2 (en) | 2013-08-20 |
US20130309820A1 (en) | 2013-11-21 |
US8859359B2 (en) | 2014-10-14 |
WO2011109149A2 (en) | 2011-09-09 |
TW201145364A (en) | 2011-12-16 |
US20110215408A1 (en) | 2011-09-08 |
WO2011109149A3 (en) | 2011-11-17 |
EP2543068A2 (en) | 2013-01-09 |
US20130011977A1 (en) | 2013-01-10 |
TWI503874B (zh) | 2015-10-11 |
CN102822972B (zh) | 2016-06-08 |
EP2543068A4 (en) | 2014-07-09 |
SG183450A1 (en) | 2012-09-27 |
US20130307042A1 (en) | 2013-11-21 |
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