JP2005136191A - 半導体集積回路装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 210000000746 body region Anatomy 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000007599 discharging Methods 0.000 claims abstract description 3
- 238000003491 array Methods 0.000 claims description 12
- 238000001514 detection method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
【解決手段】 半導体集積回路装置100は、半導体基板110と、半導体基板上に形成された絶縁層120と、絶縁層によって半導体基板から絶縁された半導体層130と、半導体層に形成されたソース領域150およびドレイン領域140と、半導体層のうちソース領域とドレイン領域との間に設けられ、電荷を蓄積または放出することによってデータを記憶することができるボディ領域160と、ボディ領域上に該ボディ領域から絶縁されるように設けられ、第1の方向へ延在するワード線WLと、ドレイン領域に接続され、第1の方向とは異なる方向に延在するビット線BLと、半導体基板および半導体層から絶縁されているように絶縁層120内に設けられ、ビット線に対して平行に延在する埋め込み配線PLとを備えている。
【選択図】 図2
Description
ビット線BL毎にセンスアンプ回路を設けると、センスアンプ回路が大きな面積を占めるので、セル占有率が低下し、チップサイズが大きくなる。これは、1T−1C型のDRAMに比べセルサイズが小さいというFBC特有の利点を損なうことを意味する。
図1は、本発明に係る第1の実施形態に従ったDRAM100のメモリ部を示したブロック図である。このメモリ部は、メモリセルアレイ10、センスアンプおよびプレートドライバ部(以下、単に、SA/PDという)20と、ロウデコーダおよびWLドライバ(以下、単に、ロウデコーダという)30と、カラムデコーダおよびCSL(Column Select Line)ドライバ(以下、単に、カラムデコーダという)40とを備えている。
図7は、本発明に係る第2の実施形態に従ったDRAM200のメモリ部を示したブロック図である。本実施形態は、センスアンプ部26およびプレートドライバ部28が分離して配置されている。本実施形態の他の構成要素は、第1の実施形態と同様であるので、その説明を省略する。
図9は、本発明に係る第3の実施形態に従ったDRAM300のメモリ部をワード線WLに沿って切断したときの断面図である。ビット線BLに沿って切断したときのDRAM300の断面図は、図3に示す断面図と同様である。図9に示す断面図は、図3のX−X線に沿って切断したときのDRAM300の断面としてよい。
図11は、本発明に係る第4の実施形態に従ったDRAM400のセンスアンプの配置および接続を示す図である。DRAM400は、メモリセルアレイ301、センスアンプ部303およびプレートドライバ部350を備えている。本実施形態は、プレートドライバ部350がセンスアンプ部303から分離して設けられている点で第3の実施形態と異なる。センスアンプ部303は、センスアンプ325〜328およびBLセレクタ322を有する。センスアンプ325〜328は、図10に示すセンスアンプ321〜324からプレートドライバを除いた形態を有する。このプレートドライバは、本実施形態においては、プレートドライバ部350として実現されている。
10 メモリセルアレイ
20 SA/PD
110 半導体基板
120 シリコン酸化膜
130 SOI層
140 ドレイン領域
150 ソース領域
160 ボディ領域
MC メモリセル
WL ワード線
PL プレート線
BL ビット線
SL ソース線
Claims (9)
- 半導体基板と、
前記半導体基板上に形成された絶縁層と、
前記絶縁層によって前記半導体基板から絶縁された半導体層と、
前記半導体層に形成された第1導電型のソース領域および第1導電型のドレイン領域と、
前記半導体層のうち前記ソース領域と前記ドレイン領域との間に設けられ、電荷を蓄積または放出することによってデータを記憶することができる第2導電型のボディ領域と、
前記ボディ領域上に該ボディ領域から絶縁されるように設けられ、第1の方向へ延在するワード線と、
前記ドレイン領域に接続され、前記第1の方向とは異なる方向に延在するビット線と、
前記半導体基板および前記半導体層から絶縁されているように前記絶縁層内に設けられ、前記ビット線に対して平行に延在する埋め込み配線とを備えた半導体集積回路装置。 - 前記ビット線はある間隔で複数本配列され、
前記埋め込み配線は前記ビット線と同一間隔で同数設けられていることを特徴とする請求項1に記載の半導体集積回路装置。 - 前記埋め込み配線は前記ワード線に対してほぼ垂直方向に延在していることを特徴とする請求項1に記載の半導体集積回路装置。
- 前記ワード線のうちの前記第1のワード線と前記埋め込み配線のうちの前記第1の埋め込み配線との交点に位置する前記ボディ領域の電荷を放出するために、前記第1のワード線の電位および前記第1の埋め込み配線の電位を同じ電位方向へ振幅させることを特徴とする請求項1に記載の半導体集積回路装置。
- 前記ワード線と前記ビット線との交点に対応して設けられた複数の前記ボディ領域からなるメモリセルアレイと、
前記メモリセルアレイの周辺のうち第1の側辺近傍に設けられ、前記メモリセルアレイ内の前記ボディ領域内のデータを検出することができる検出回路と、
前記第1の側辺近傍に設けられ、前記埋め込み配線を駆動する駆動回路とをさらに備えたことを特徴とする請求項1から請求項4のいずれかに記載の半導体集積回路装置。 - 前記ワード線と前記ビット線との交点に対応して設けられた複数の前記ボディ領域からなるメモリセルアレイと、
前記メモリセルアレイの周辺のうち第1の側辺近傍に設けられ、前記メモリセルアレイ内の前記ボディ領域内のデータを検出することができる検出回路と、
前記メモリセルアレイの周辺のうち前記第1の側辺に対して反対側にある第2の側辺近傍に設けられ、前記埋め込み配線を駆動する駆動回路とをさらに備えたことを特徴とする請求項1から請求項4のいずれかに記載の半導体集積回路装置。 - 複数の前記メモリセルアレイが並んで配列されており、
前記検出回路および前記駆動回路が、隣り合う前記メモリセルアレイの間に交互に設けられていることを特徴とする請求項6に記載の半導体集積回路装置。 - 前記埋め込み配線は、複数の前記ビット線に対して1つずつ対応して設けられていることを特徴とする請求項1から請求項6のいずれかに記載の半導体集積回路装置。
- 前記ボディ領域は、フルディプレッション型のメモリセルの一部を構成することを特徴とする請求項1に記載の記載の半導体集積回路装置。
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JP2003370696A JP4044510B2 (ja) | 2003-10-30 | 2003-10-30 | 半導体集積回路装置 |
US10/779,621 US6882008B1 (en) | 2003-10-30 | 2004-02-18 | Semiconductor integrated circuit device |
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JP2003370696A JP4044510B2 (ja) | 2003-10-30 | 2003-10-30 | 半導体集積回路装置 |
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JP4044510B2 JP4044510B2 (ja) | 2008-02-06 |
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Cited By (12)
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JP2009117518A (ja) * | 2007-11-05 | 2009-05-28 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
JP2012256822A (ja) * | 2010-09-14 | 2012-12-27 | Semiconductor Energy Lab Co Ltd | 記憶装置及び半導体装置 |
JP2013521651A (ja) * | 2010-03-02 | 2013-06-10 | マイクロン テクノロジー, インク. | 浮遊ボディセル、浮遊ボディセルを含むデバイス、ならびに浮遊ボディセルの形成方法。 |
US8809145B2 (en) | 2010-03-02 | 2014-08-19 | Micron Technology, Inc. | Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same |
US8980699B2 (en) | 2010-03-02 | 2015-03-17 | Micron Technology, Inc. | Thyristor-based memory cells, devices and systems including the same and methods for forming the same |
US9129983B2 (en) | 2011-02-11 | 2015-09-08 | Micron Technology, Inc. | Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor |
US9269795B2 (en) | 2011-07-26 | 2016-02-23 | Micron Technology, Inc. | Circuit structures, memory circuitry, and methods |
US9361966B2 (en) | 2011-03-08 | 2016-06-07 | Micron Technology, Inc. | Thyristors |
US9608119B2 (en) | 2010-03-02 | 2017-03-28 | Micron Technology, Inc. | Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures |
US9646869B2 (en) | 2010-03-02 | 2017-05-09 | Micron Technology, Inc. | Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices |
US10373956B2 (en) | 2011-03-01 | 2019-08-06 | Micron Technology, Inc. | Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors |
US12040042B2 (en) | 2010-09-14 | 2024-07-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including transistor |
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JP4110115B2 (ja) * | 2004-04-15 | 2008-07-02 | 株式会社東芝 | 半導体記憶装置 |
KR100745902B1 (ko) * | 2005-10-24 | 2007-08-02 | 주식회사 하이닉스반도체 | 비휘발성 강유전체 메모리 장치 |
KR100663368B1 (ko) * | 2005-12-07 | 2007-01-02 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 데이터 라이트 및 리드방법 |
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JP4077381B2 (ja) * | 2003-08-29 | 2008-04-16 | 株式会社東芝 | 半導体集積回路装置 |
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US6882008B1 (en) | 2005-04-19 |
US20050093064A1 (en) | 2005-05-05 |
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