JP4469744B2 - 半導体記憶装置および半導体記憶装置の駆動方法 - Google Patents
半導体記憶装置および半導体記憶装置の駆動方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 36
- 238000000034 method Methods 0.000 title description 5
- 210000000746 body region Anatomy 0.000 claims description 70
- 230000014759 maintenance of location Effects 0.000 claims description 21
- 230000005684 electric field Effects 0.000 claims description 11
- 239000010410 layer Substances 0.000 description 71
- 239000000758 substrate Substances 0.000 description 7
- 238000004088 simulation Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000007599 discharging Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/4016—Memory devices with silicon-on-insulator cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Description
前記ボディ領域内の蓄積電荷が少ない状態を示すデータ状態の書込みからデータ保持状態へ移行する際に、前記ソース層の電位を前記ゲート電極の電位のシフト方向と同じ電位方向へ変化させることによって、前記ボディ領域と前記ソース層との間の接合部にかかる逆方向電界を小さくすることを特徴とする。
図1は、本発明に係る第1の実施形態に従ったFBCメモリ100(以下、メモリ100ともいう)の平面図である。メモリ100の周辺部には、メモリ100を制御するための周辺回路(図示せず)が設けられていてもよい。
図6は、本発明に係る第2の実施形態に従ったFBCメモリ100の動作を示すタイミングチャートである。第1の実施形態では、データの読出し時(時間T3)において、ソース電圧はデータ保持時のソース電圧を維持していた。従って、上述のように、メモリセルの閾値電圧差ΔVtが低下してしまった。そこで、第2の実施形態では、データの読出し時において、ソース電圧VSROを、データ保持時のソース電圧VSRよりもデータの読出し時のゲート電圧VGROに近づける。
図7は、本発明に係る第3の実施形態に従ったFBCメモリ100の動作を示すタイミングチャートである。第2の実施形態では、データの読出し時(時間T3)におけるゲート電圧VGROがデータの書込み時(時間T1、T4)におけるゲート電圧VGWと同じであった。
WL ワード線
BL ビット線
SL ソース線
5 半導体基板
7 BOX層
10 半導体層(SOI層)
20 ソース層
30 ドレイン層
40 ボディ領域
50 ゲート絶縁膜
60 ゲート電極
VGW データ書込み時のゲート電圧
VSW データ書込み時のソース電圧
VDW データ書込み時のドレイン電圧
VGR データ保持時のゲート電圧
VSR データ保持時のソース電圧
VDR データ保持時のドレイン電圧
VGRO データ読出し時のゲート電圧
VSRO データ読出し時のソース電圧
VDRO データ読出し時のドレイン電圧
Claims (5)
- 半導体層と、
前記半導体層内に設けられたソース層と、
前記半導体層内に設けられたドレイン層と、
前記ソース層と前記ドレイン層との間の前記半導体層に設けられたボディ領域と、
前記ボディ領域上に設けられたゲート絶縁膜と、
前記ゲート絶縁膜上に設けられたゲート電極とを備え、
前記ボディ領域に電荷を蓄積または放出することによってデータの書込みまたはデータの読出しが可能であり、
前記ボディ領域内の蓄積電荷が多い状態を示すデータ状態の書込みからデータ保持状態へ移行する際に、前記ソース層の電位VSWおよび前記ドレイン層の電位VDWを前記ゲート電極の電位のシフト方向と同じ電位方向へ変化させることによって、データ保持時の前記ソース層の電位VSRおよび前記ドレイン層の電位VDRとデータ保持時の前記ゲート電極の電位VGRとの差を、それぞれ前記書込み時の前記ソース層の電位VSWおよび前記ドレイン層の電位VDWと前記電位VGRとの差よりも小さくし、データ保持時の前記ソース層の電位VSRを、前記ボディ領域内の蓄積電荷が多い状態を示すデータを保持する前記ボディ領域の電位にほぼ等しくし、
前記ボディ領域内の蓄積電荷が少ない状態を示すデータ状態の書込みからデータ保持状態へ移行する際に、前記ソース層の電位を前記ゲート電極の電位のシフト方向と同じ電位方向へ変化させることによって、前記ボディ領域と前記ソース層との間の接合部にかかる逆方向電界を小さくすることを特徴とする半導体記憶装置。 - データ保持状態からデータ読出しへ移行する際に、前記ソース層の電位VSRおよび前記ドレイン層の電位VDRを前記ゲート電極の電位のシフト方向と同じ電位方向へ変化させることによって、データの読出し時の前記ソース層の電位VSROおよび前記ドレイン層の電位VDROとデータの読出し時の前記ゲート電極の電位VGROとの差を、データ保持時の前記ソース層の電位VSRおよび前記ドレイン層の電位VDRと前記電位VGROとの差よりも小さくすることを特徴とする請求項1に記載の半導体記憶装置。
- データ読出し時の前記ゲート電極の電位は、データ書込み時の前記ゲート電極の電位よりも、データ読出し時における前記ソース層の電位に近いことを特徴とする請求項1に記載の半導体記憶装置。
- 前記半導体層、前記ソース層、前記ドレイン層、前記ボディ領域、前記ゲート絶縁膜、前記ゲート電極を含み、第1の方向に配列された複数のメモリセルと、
前記第1の方向に沿って延伸し、複数の前記ドレイン層に接続されたビット線と、
前記第1の方向に交差する第2の方向に延伸し、前記ゲート電極に接続された複数のワード線と、
前記第2の方向に延伸し、前記ソース層に接続された複数のソース線と、を備え、
前記ボディ領域内の蓄積電荷が少ない状態を示すデータ状態の書込み時に、前記複数のソース線のうち選択ソース線に前記電位VSWを与え、前記複数のソース線のうち非選択ソース線に前記電位VSRを与えることを特徴とする請求項1に記載の半導体記憶装置。 - 前記ソース線は隣接する2本のワード線に共有されており、
前記ボディ領域内の蓄積電荷が少ない状態を示すデータ状態の書込み時に、前記選択ソース線に対応する前記隣接する2本のワード線のうち非選択ワード線の電位を他の非選択ワード線の電位よりも低くすることを特徴とする請求項4に記載の半導体記憶装置。
Priority Applications (2)
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JP2005079795A JP4469744B2 (ja) | 2005-03-18 | 2005-03-18 | 半導体記憶装置および半導体記憶装置の駆動方法 |
US11/236,671 US7463523B2 (en) | 2005-03-18 | 2005-09-28 | Semiconductor memory device and method of driving a semiconductor memory device |
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JP2005079795A JP4469744B2 (ja) | 2005-03-18 | 2005-03-18 | 半導体記憶装置および半導体記憶装置の駆動方法 |
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JP2006260722A JP2006260722A (ja) | 2006-09-28 |
JP4469744B2 true JP4469744B2 (ja) | 2010-05-26 |
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Families Citing this family (21)
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US7606066B2 (en) * | 2005-09-07 | 2009-10-20 | Innovative Silicon Isi Sa | Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same |
JP2007242950A (ja) * | 2006-03-09 | 2007-09-20 | Toshiba Corp | 半導体記憶装置 |
JP2008117489A (ja) * | 2006-11-07 | 2008-05-22 | Toshiba Corp | 半導体記憶装置 |
JP5500771B2 (ja) * | 2006-12-05 | 2014-05-21 | 株式会社半導体エネルギー研究所 | 半導体装置及びマイクロプロセッサ |
JP4791986B2 (ja) * | 2007-03-01 | 2011-10-12 | 株式会社東芝 | 半導体記憶装置 |
JP2009032384A (ja) * | 2007-06-29 | 2009-02-12 | Toshiba Corp | 半導体記憶装置の駆動方法および半導体記憶装置 |
US7652910B2 (en) * | 2007-06-30 | 2010-01-26 | Intel Corporation | Floating body memory array |
KR20090116088A (ko) | 2008-05-06 | 2009-11-11 | 삼성전자주식회사 | 정보 유지 능력과 동작 특성이 향상된 커패시터리스 1t반도체 메모리 소자 |
US7969808B2 (en) | 2007-07-20 | 2011-06-28 | Samsung Electronics Co., Ltd. | Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same |
KR101308048B1 (ko) | 2007-10-10 | 2013-09-12 | 삼성전자주식회사 | 반도체 메모리 장치 |
KR100900136B1 (ko) * | 2007-10-17 | 2009-06-01 | 주식회사 하이닉스반도체 | 1-트랜지스터형 디램 |
KR100892731B1 (ko) * | 2008-01-02 | 2009-04-10 | 주식회사 하이닉스반도체 | 1-트랜지스터형 디램 구동 방법 |
KR100892732B1 (ko) * | 2008-01-02 | 2009-04-10 | 주식회사 하이닉스반도체 | 1-트랜지스터형 디램 구동 방법 |
KR20090075063A (ko) | 2008-01-03 | 2009-07-08 | 삼성전자주식회사 | 플로팅 바디 트랜지스터를 이용한 동적 메모리 셀을 가지는메모리 셀 어레이를 구비하는 반도체 메모리 장치 및 이장치의 동작 방법 |
JP5121475B2 (ja) * | 2008-01-28 | 2013-01-16 | 株式会社東芝 | 半導体記憶装置 |
JP2009205724A (ja) * | 2008-02-27 | 2009-09-10 | Toshiba Corp | 半導体記憶装置 |
KR20100070158A (ko) | 2008-12-17 | 2010-06-25 | 삼성전자주식회사 | 커패시터가 없는 동작 메모리 셀을 구비한 반도체 메모리 장치 및 이 장치의 동작 방법 |
KR101442177B1 (ko) | 2008-12-18 | 2014-09-18 | 삼성전자주식회사 | 커패시터 없는 1-트랜지스터 메모리 셀을 갖는 반도체소자의 제조방법들 |
JP2010157283A (ja) * | 2008-12-26 | 2010-07-15 | Toshiba Corp | 半導体記憶装置 |
US8148780B2 (en) | 2009-03-24 | 2012-04-03 | Micron Technology, Inc. | Devices and systems relating to a memory cell having a floating body |
US7929343B2 (en) * | 2009-04-07 | 2011-04-19 | Micron Technology, Inc. | Methods, devices, and systems relating to memory cells having a floating body |
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US6621725B2 (en) | 2000-08-17 | 2003-09-16 | Kabushiki Kaisha Toshiba | Semiconductor memory device with floating storage bulk region and method of manufacturing the same |
JP4216483B2 (ja) | 2001-02-15 | 2009-01-28 | 株式会社東芝 | 半導体メモリ装置 |
JP4383718B2 (ja) | 2001-05-11 | 2009-12-16 | 株式会社東芝 | 半導体メモリ装置及びその製造方法 |
JP2004335797A (ja) * | 2003-05-08 | 2004-11-25 | Sharp Corp | 半導体記憶装置とその駆動方法、および携帯電子機器 |
JP4105031B2 (ja) * | 2003-05-16 | 2008-06-18 | シャープ株式会社 | 補聴器 |
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2005
- 2005-03-18 JP JP2005079795A patent/JP4469744B2/ja not_active Expired - Fee Related
- 2005-09-28 US US11/236,671 patent/US7463523B2/en not_active Expired - Fee Related
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US20060208301A1 (en) | 2006-09-21 |
JP2006260722A (ja) | 2006-09-28 |
US7463523B2 (en) | 2008-12-09 |
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