JP2013118215A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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Abstract
【解決手段】ダイパッド2dと、ダイパッド2d上に搭載された半導体チップ1と、半導体チップ1の周囲に配置された複数のリード2aと、半導体チップ1の複数の電極パッド1cと複数のリード2aとを電気的に接続する複数のワイヤ3と、半導体チップ1及び複数のワイヤ3を封止する封止体4とを有するQFN5において、各リード2aの左右両側のずれた位置に段差部2n,2pを形成して、隣り合うリード2aとの段差部2n,2pの位置をずらすことで、リード間の隙間を小さくしてQFN5の小型化または多ピン化を実現する。
【選択図】図2
Description
図1は本発明の実施の形態1の半導体装置の構造の一例を示す平面図、図2は図1の半導体装置の構造を封止体を透過して示す平面図、図3は図1の半導体装置の構造の一例を示す裏面図、図4は図1の半導体装置の構造の一例を示す側面図、図5は図2のA−A線に沿って切断した構造の一例を示す断面図である。また、図6は図2のW部の構造を示す拡大部分平面図、図7は図6のC−C線に沿って切断した構造の一例を示す断面図、図8は図6のD−D線に沿って切断した構造の一例を示す断面図、図9は図6のE−E線に沿って切断した構造の一例を示す断面図、図10は図6のF−F線に沿って切断した構造の一例を示す断面図である。
図26は本発明の実施の形態2の半導体装置の構造の一例を封止体を透過して示す平面図である。
1a 表面(主面)
1b 裏面
1c 電極パッド
2 リードフレーム
2a リード
2aa 上面
2ab 下面
2b アウター部
2c,2ca 吊りリード
2d ダイパッド
2da 上面
2db 下面
2e インナー部
2f 外側端面
2g 内側端面
2h,2i 側面
2j 中央リード
2k 先端部
2m 後端部
2n,2p,2q 段差部
2r 迫り出し面
2s デバイス領域
2t 枠部
2u 幅広部
2v ワイヤ接合部
2w 延在方向
3 ワイヤ
4 封止体
4a 側面
4b 下面
4c 一括封止体
5 QFN(半導体装置)
6 ダイボンド材
7 中心線
8 延在方向
9 ブレード
10 ダイシングテープ
11 QFN(半導体装置)
Claims (10)
- ダイパッドと、
前記ダイパッドを支持する複数の吊りリードと、
前記複数の吊りリードの間に配置された複数のリードと、
主面、前記主面に形成された複数の電極パッド、および前記主面とは反対側の裏面を有し、かつ前記ダイパッドの上面に搭載された半導体チップと、
前記半導体チップの前記複数の電極パッドと前記複数のリードとをそれぞれ電気的に接続する複数のワイヤと、
前記複数のリードのそれぞれの下面が露出するように、前記半導体チップおよび前記複数のワイヤを封止する封止体と、
を含み、
前記複数のリードのそれぞれは、前記封止体から露出する前記下面、前記下面とは反対側の上面、前記上面と前記下面との間に位置し、かつ前記ダイパッドと対向する内側端面、前記内側端面とは反対側に位置し、かつ前記封止体から露出する外側端面、前記上面と前記下面との間に位置し、かつ前記内側端面と前記外側端面との間に位置する第1側面、前記第1側面とは反対側の第2側面を有しており、
さらに、前記複数のリードのそれぞれは、前記複数のリードのそれぞれの延在方向において、前記内側端面側に位置する第1部分と、前記第1部分よりも前記外側端面側に位置する第2部分と、を有しており、
前記第1側面における前記第1部分で、かつ前記下面よりも前記上面側には、第1段差部が形成されており、
前記第2側面における前記第2部分であって、前記下面よりも前記上面側には、第2段差部が形成されており、
前記第1側面における前記第2部分には、前記第1および第2段差部は形成されていなく、
前記第2側面における前記第1部分には、前記第1および第2段差部は形成されていないことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれの前記第1部分における前記下面には、前記内側端面に連なる第3段差部が形成されていることを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記第3段差部の前記ダイパッド方向への迫り出し量は、前記第1段差部の隣り合った前記リード方向への迫り出し量、および前記第2段差部の隣り合った前記リード方向への迫り出し量よりそれぞれ大きいことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記封止体の平面形状は、四角形からなり、前記複数のリードは、平面視において、前記封止体の各辺に沿って奇数本ずつ配置され、
前記各辺において、前記奇数本の前記リードにおける中央リードを線対称とした形態になるように、前記複数のリードのそれぞれの前記第1及び前記第2段差部が形成されていることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記中央リードの内側端部には、平面視で幅広となる幅広部が形成されていることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記第1段差部が形成された前記第1側面は、前記ワイヤの延在方向側であることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記各辺の前記奇数本の前記リードのうち、前記中央に配置される前記リード以外のリードは、それぞれの前記リードの内側端部の平面視の形状が、前記ワイヤの延在方向に沿うように屈曲していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記封止体の平面形状は、四角形からなり、前記複数のリードは、平面視において、前記封止体の各辺に沿って偶数本ずつ配置され、
前記各辺において、前記偶数本の前記リードは、各リードの前記第1及び前記第2段差部が前記偶数本の前記リードの配列方向に対してそれぞれ同一の向きに形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれは、エッチング加工によって形成されたものであることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれの前記第2側面の前記第2部分に形成された前記第2段差部は、前記封止体の内部で終端していることを特徴とする半導体装置。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018018953A (ja) * | 2016-07-28 | 2018-02-01 | 株式会社東海理化電機製作所 | 半導体装置の製造方法 |
JP2019192947A (ja) * | 2013-07-31 | 2019-10-31 | 日亜化学工業株式会社 | リードフレーム、樹脂付きリードフレーム、樹脂パッケージ、発光装置及び樹脂パッケージの製造方法 |
JP2020170736A (ja) * | 2019-04-01 | 2020-10-15 | 富士電機株式会社 | 半導体装置 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5798021B2 (ja) * | 2011-12-01 | 2015-10-21 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN104347570B (zh) * | 2013-07-26 | 2018-07-20 | 恩智浦美国有限公司 | 无引线型半导体封装及其组装方法 |
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KR102457011B1 (ko) * | 2015-06-24 | 2022-10-21 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치의 제조 방법 |
JP2017045944A (ja) * | 2015-08-28 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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JP6695156B2 (ja) * | 2016-02-02 | 2020-05-20 | エイブリック株式会社 | 樹脂封止型半導体装置 |
CN107195612A (zh) * | 2017-06-20 | 2017-09-22 | 南京矽邦半导体有限公司 | 一种基于加长半蚀刻拱形内引脚qfn框架及其封装芯片 |
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003174136A (ja) * | 2001-12-07 | 2003-06-20 | Aoi Electronics Co Ltd | 樹脂モールド半導体装置 |
JP2003188331A (ja) * | 2001-12-19 | 2003-07-04 | Mitsui High Tec Inc | リードフレームおよびこれを用いた半導体装置 |
JP2004022725A (ja) * | 2002-06-14 | 2004-01-22 | Renesas Technology Corp | 半導体装置 |
JP2004207615A (ja) * | 2002-12-26 | 2004-07-22 | Mitsui High Tec Inc | リードフレーム |
JP2008198718A (ja) * | 2007-02-09 | 2008-08-28 | Asmo Co Ltd | 樹脂封止型半導体装置 |
US20090079051A1 (en) * | 2007-09-20 | 2009-03-26 | Kenji Amano | Semiconductor device and manufacturing method of the same |
JP2011086811A (ja) * | 2009-10-16 | 2011-04-28 | Apic Yamada Corp | リードフレーム、電子部品用基板及び電子部品 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030006055A1 (en) * | 2001-07-05 | 2003-01-09 | Walsin Advanced Electronics Ltd | Semiconductor package for fixed surface mounting |
JP4417150B2 (ja) * | 2004-03-23 | 2010-02-17 | 株式会社ルネサステクノロジ | 半導体装置 |
US7375416B2 (en) * | 2005-09-20 | 2008-05-20 | United Test And Assembly Center Ltd. | Leadframe enhancement and method of producing a multi-row semiconductor package |
JP5155644B2 (ja) * | 2007-07-19 | 2013-03-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20090032917A1 (en) * | 2007-08-02 | 2009-02-05 | M/A-Com, Inc. | Lead frame package apparatus and method |
JP2010177272A (ja) | 2009-01-27 | 2010-08-12 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
US8802500B2 (en) * | 2009-11-11 | 2014-08-12 | Stats Chippac Ltd. | Integrated circuit packaging system with leads and method of manufacture thereof |
TWM393039U (en) * | 2010-04-29 | 2010-11-21 | Kun Yuan Technology Co Ltd | Wire holder capable of reinforcing sealing connection and packaging structure thereof |
TWI489607B (zh) * | 2010-11-23 | 2015-06-21 | 登豐微電子股份有限公司 | 封裝結構 |
JP5798021B2 (ja) * | 2011-12-01 | 2015-10-21 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2011
- 2011-12-01 JP JP2011263744A patent/JP5798021B2/ja not_active Expired - Fee Related
-
2012
- 2012-09-27 TW TW101135676A patent/TWI540691B/zh not_active IP Right Cessation
- 2012-11-12 CN CN201210470646.7A patent/CN103137592B/zh active Active
- 2012-11-12 CN CN2012206136162U patent/CN202996818U/zh not_active Expired - Fee Related
- 2012-11-27 KR KR1020120134989A patent/KR101953393B1/ko active IP Right Grant
- 2012-12-03 US US13/692,286 patent/US8836106B2/en active Active
-
2014
- 2014-08-21 US US14/465,379 patent/US9443794B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003174136A (ja) * | 2001-12-07 | 2003-06-20 | Aoi Electronics Co Ltd | 樹脂モールド半導体装置 |
JP2003188331A (ja) * | 2001-12-19 | 2003-07-04 | Mitsui High Tec Inc | リードフレームおよびこれを用いた半導体装置 |
JP2004022725A (ja) * | 2002-06-14 | 2004-01-22 | Renesas Technology Corp | 半導体装置 |
JP2004207615A (ja) * | 2002-12-26 | 2004-07-22 | Mitsui High Tec Inc | リードフレーム |
JP2008198718A (ja) * | 2007-02-09 | 2008-08-28 | Asmo Co Ltd | 樹脂封止型半導体装置 |
US20090079051A1 (en) * | 2007-09-20 | 2009-03-26 | Kenji Amano | Semiconductor device and manufacturing method of the same |
JP2009076658A (ja) * | 2007-09-20 | 2009-04-09 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2011086811A (ja) * | 2009-10-16 | 2011-04-28 | Apic Yamada Corp | リードフレーム、電子部品用基板及び電子部品 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019192947A (ja) * | 2013-07-31 | 2019-10-31 | 日亜化学工業株式会社 | リードフレーム、樹脂付きリードフレーム、樹脂パッケージ、発光装置及び樹脂パッケージの製造方法 |
JP2018018953A (ja) * | 2016-07-28 | 2018-02-01 | 株式会社東海理化電機製作所 | 半導体装置の製造方法 |
WO2018020864A1 (ja) * | 2016-07-28 | 2018-02-01 | 株式会社東海理化電機製作所 | 半導体装置の製造方法 |
CN109564879A (zh) * | 2016-07-28 | 2019-04-02 | 株式会社东海理化电机制作所 | 半导体装置的制造方法 |
JP2020170736A (ja) * | 2019-04-01 | 2020-10-15 | 富士電機株式会社 | 半導体装置 |
JP7338204B2 (ja) | 2019-04-01 | 2023-09-05 | 富士電機株式会社 | 半導体装置 |
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