JP6164895B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6164895B2 JP6164895B2 JP2013076787A JP2013076787A JP6164895B2 JP 6164895 B2 JP6164895 B2 JP 6164895B2 JP 2013076787 A JP2013076787 A JP 2013076787A JP 2013076787 A JP2013076787 A JP 2013076787A JP 6164895 B2 JP6164895 B2 JP 6164895B2
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- wire
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- semiconductor device
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- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
図1は実施の形態の半導体装置の構造の一例を示す平面図、図2は図1に示す半導体装置の構造を封止体を透過して示す平面図、図3は図2に示すA−A線に沿って切断した構造を示す断面図、図4は図2に示すB−B線に沿って切断した構造を示す断面図である。さらに、図5は図1に示す半導体装置におけるワイヤリング状態の一例を示す部分拡大平面図、図6は図5に示すA−A線に沿って切断した構造を示す部分拡大断面図である。
1a インナリード(第1リード、電極)
1b インナリード(第2リード、電極)
1c ダイパッド(アイランド、支持体)
1ca 上面(チップ搭載面)
1cb 下面(裏面)
1cc ディンプル部
1cd めっき塗布部
1d バスバー(共通リード、共通電極、電極)
1da バスバー領域(共通リード領域、共通電極領域)
1db リード部分(電極部分)
1e 吊りリード
1ea 基準吊りリード
1eb 折り曲げ部
1f アウタリード(一部、電極端子、外部電極端子)
1g デバイス領域
1h 枠部
1i スリット孔
2 半導体チップ
2a 主面
2b 裏面
2c 電極パッド(電極)
3 封止体
3a 表面
3b 実装面(裏面)
3c 側面
4 ワイヤ(導電体)
4a 第1ワイヤ(第1導電体)
4b 第2ワイヤ(第2導電体)
4c 第3ワイヤ(第3導電体)
4d 第4ワイヤ(第4導電体)
4e 第5ワイヤ(第5導電体)
5 QFP(Quad Flat Package、半導体装置)
6 ダイボンド材(積層接着剤、ダイボンドフィルム、DAF(Die Attach Film))
7 テープ材
8 流動方向
10 封止樹脂(樹脂)
11 空間部
12 樹脂成型金型(成型金型)
12a 上型
12aa キャビティ
12ab ゲート
12b 下型
12ba キャビティ
12c プランジャ
12d ランナ
13 QFP(Quad Flat Package、半導体装置)
Claims (8)
- (a)チップ搭載面、第1辺および前記第1辺と交差する第2辺を有する矩形状のダイパッドと、前記ダイパッドを支持する複数の吊りリードと、前記ダイパッドの周囲に配置された複数の第1リードと、前記複数の第1リードのそれぞれより長さが短い複数の第2リードと、平面視で前記ダイパッドと前記複数の第2リードとの間に複数のリード同士を繋ぐリード部分が配置され、かつ前記複数の第2リードを囲むように形成された共通リードとを備えたリードフレームを準備する工程、
(b)主面、第3辺および前記第3辺とは反対側の第4辺を有し、前記主面に複数の電極パッドが形成された矩形状の半導体チップを前記ダイパッドの前記チップ搭載面上に搭載する工程、
(c)前記半導体チップの前記複数の電極パッドと、前記共通リード、前記複数の第1リードおよび前記複数の第2リードのそれぞれとを、複数のワイヤを介して電気的に接続する工程、
(d)前記複数の第1、第2リードおよび前記共通リードのそれぞれの一部が封止体から露出するように、前記共通リード、前記半導体チップおよび前記複数のワイヤを樹脂で封止する工程、
(e)前記封止体から露出する複数のアウタリードのそれぞれを、前記リードフレームから切り離す工程、
を有し、
前記(a)工程において、
前記複数の吊りリードのうち、樹脂封止時に前記樹脂を供給するゲートに対応した位置の基準吊りリードは、前記基準吊りリードの一端が前記ダイパッドの前記第1辺と前記第2辺との交差部に接続されており、
前記(b)工程において、
前記ダイパッドは、平面視において前記半導体チップより大きく、
前記半導体チップの前記第3辺は、平面視において前記ダイパッドの第1辺と対向し、かつ平面視において前記半導体チップの前記第4辺と前記ダイパッドの前記第1辺の間に設置されており、
前記複数の電極パッドは、前記第3辺に沿って配置された複数の第1電極パッド、複数の第2電極パッドおよび複数の第3電極パッドを含み、
前記(c)工程において、
前記複数のワイヤのうちの複数の第1ワイヤによって前記複数の第1電極パッドと前記複数の第1リードとを電気的に接続し、
前記複数のワイヤのうちの複数の第2ワイヤによって前記複数の第2電極パッドと前記複数の第2リードの何れかのリードとを前記共通リードを飛び越えて電気的に接続し、
前記複数のワイヤのうちの複数の第3ワイヤによって前記複数の第3電極パッドと前記複数の第2リードの何れかの他のリードとを前記共通リードを飛び越えて、かつ前記複数の第3ワイヤのそれぞれのループ高さを前記複数の第2ワイヤのそれぞれのループ高さより高くして電気的に接続し、
前記基準吊りリードに対して、前記共通リードに応じた共通リード領域において前記複数の第2ワイヤは、前記複数の第3ワイヤより近くに配置されており、
前記複数の第3ワイヤは、前記ダイパッドの前記第1辺の延在方向において前記複数の第1ワイヤよりも前記基準吊りリードの近くに配置されており、
前記複数の第3ワイヤのそれぞれのループ高さは、前記複数の第2ワイヤのそれぞれのループ高さより高い、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(c)工程で、
前記共通リード領域において前記第2ワイヤの前記基準吊りリード側に、前記第2ワイヤよりループ高さが低い第4ワイヤを前記第2ワイヤに近接して配置して前記共通リードに電気的に接続する、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記(c)工程で、
前記共通リード領域において前記第4ワイヤの前記基準吊りリード側に、何れの前記ワイヤも接続されない前記半導体チップの前記電極パッドが設けられている、半導体装置の製造方法。 - 請求項3に記載の半導体装置の製造方法において、
前記(c)工程で、
前記第2ワイヤは、前記共通リード領域において前記基準吊りリード寄りの最も端部の位置の前記第2リードに電気的に接続する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(c)工程で、
前記共通リード領域において前記第2ワイヤに隣接して、かつループ高さを前記第2ワイヤより低くして前記第2ワイヤより前記基準吊りリードの近くに第4ワイヤを配置して
前記共通リードに前記第4ワイヤを電気的に接続する、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記(c)工程で、
前記ダイパッドに、前記第4ワイヤよりループ高さが低い第5ワイヤを電気的に接続する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記ワイヤは、銅を主成分とする材料から成る、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記複数の第1ワイヤのそれぞれのループ高さは、複数の前記第4ワイヤのそれぞれのループ高さと実質的に同じ高さである、半導体装置の製造方法。
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US14/219,813 US20140291826A1 (en) | 2013-04-02 | 2014-03-19 | Semiconductor device manufacturing method and semiconductor device |
CN201410131172.2A CN104103534B (zh) | 2013-04-02 | 2014-04-02 | 半导体器件制造方法 |
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US9972557B2 (en) | 2014-12-11 | 2018-05-15 | Stmicroelectronics Pte Ltd | Integrated circuit (IC) package with a solder receiving area and associated methods |
US10847488B2 (en) | 2015-11-02 | 2020-11-24 | Mediatek Inc. | Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires |
CN110954034B (zh) * | 2019-12-12 | 2021-06-11 | 深圳赛意法微电子有限公司 | 一种半导体器件的导线线弧高度测量方法 |
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JPH06302638A (ja) * | 1993-04-16 | 1994-10-28 | Sony Corp | 半導体装置 |
JPH09266223A (ja) * | 1996-03-28 | 1997-10-07 | Nec Kyushu Ltd | 半導体装置 |
JPH10326802A (ja) * | 1997-05-26 | 1998-12-08 | Seiko Epson Corp | 半導体装置の製造方法 |
US6545347B2 (en) * | 2001-03-06 | 2003-04-08 | Asat, Limited | Enhanced leadless chip carrier |
US20020153600A1 (en) * | 2001-04-19 | 2002-10-24 | Walton Advanced Electronics Ltd | Double sided chip package |
DE102005035083B4 (de) * | 2004-07-24 | 2007-08-23 | Samsung Electronics Co., Ltd., Suwon | Bondverbindungssystem, Halbleiterbauelementpackung und Drahtbondverfahren |
US7132735B2 (en) * | 2005-03-07 | 2006-11-07 | Agere Systems Inc. | Integrated circuit package with lead fingers extending into a slot of a die paddle |
JP2007180077A (ja) * | 2005-12-27 | 2007-07-12 | Renesas Technology Corp | 半導体装置 |
US7816186B2 (en) * | 2006-03-14 | 2010-10-19 | Unisem (Mauritius) Holdings Limited | Method for making QFN package with power and ground rings |
TW200820402A (en) * | 2006-10-26 | 2008-05-01 | Chipmos Technologies Inc | Stacked chip packaging with heat sink struct |
US8283757B2 (en) * | 2007-07-18 | 2012-10-09 | Mediatek Inc. | Quad flat package with exposed common electrode bars |
US7737537B2 (en) * | 2007-12-12 | 2010-06-15 | Infineon Technologies Ag | Electronic device |
JP5130566B2 (ja) * | 2008-07-01 | 2013-01-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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