JP2010278308A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2010278308A JP2010278308A JP2009130653A JP2009130653A JP2010278308A JP 2010278308 A JP2010278308 A JP 2010278308A JP 2009130653 A JP2009130653 A JP 2009130653A JP 2009130653 A JP2009130653 A JP 2009130653A JP 2010278308 A JP2010278308 A JP 2010278308A
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
【解決手段】本発明の半導体装置では、半導体素子24が実装されるアイランド12の周囲に放射状の接続リード16が配置されている。また、アイランド12の4隅からは外部に吊りリード14A−14Dが延在している。そして、接続リード16および吊りリード14A−14Dの上面には、帯状の支持テープ18A−18Dが貼着されている。支持テープ18A−18Dを介して、接続リード16は吊りリード14A−14Dに固定される。更に、支持テープ18A−18Dは、接続リード16の中間部付近の上面に貼着されているので、接続リード16の先端部に金属細線22を接続することが可能となる。このことにより、金などの高価な金属材料から成る金属細線22の線長が短縮化されるので、材料に係るコストが低減される。
【選択図】図1
Description
12 アイランド
14、14A、14B、14C、14D 吊りリード
16、16A、16B 接続リード
18、18A、18B、18C、18D 支持テープ
20 封止樹脂
22 金属細線
24 半導体素子
30 リードフレーム
32 ユニット
34 連結条帯
36 連結条帯
38 タイバー
40 モールド金型
42 上金型
44 下金型
46 キャビティ
Claims (8)
- アイランドと、
前記アイランドから連続する吊りリードと、
一端が前記アイランドの近傍に配置されると共に、他端が外部に露出する接続リードと、
前記アイランドの上面に固着された半導体素子と、
一端が前記半導体素子の電極に接続されると共に、他端が前記接続リードの上面に接続される金属細線と、
前記吊りリードの上面および前記接続リードの上面に貼着される支持テープと、
前記半導体素子、前記金属細線、前記アイランド、前記接続リード、前記吊りリードおよび前記支持テープを被覆する封止樹脂と、を備え、
前記金属細線の他端は、前記支持テープが貼着される箇所よりも前記半導体素子側の前記接続リードの上面に接続されることを特徴とする半導体装置。 - 前記吊りリードは、四角形状の前記アイランドの4隅から外側に向かって延在し、
前記支持テープは、前記アイランドが備える4つの側辺に対応して4つが設けられ、
各々の前記支持テープは、両端が前記吊りリードの上面に貼着されると共に、中間部が前記接続リードの上面に貼着されることを特徴とする請求項1記載の半導体装置。 - 各々の前記支持テープの端部は、他の前記支持テープと重畳しない箇所の前記支持リードの上面に貼着されることを特徴とする請求項2記載の半導体装置。
- 前記支持テープは、平面視で端部が中間部よりも内側に位置する湾曲形状を呈することを特徴とする請求項3記載の半導体装置。
- 前記支持テープは、前記アイランドを一方向に挟むように配置された一対の第1支持テープと、前記アイランドを他方向に挟むように配置された一対の第2支持テープからなり、
前記第1支持テープの形状と前記第2支持テープの形状とは異なることを特徴とする請求項4記載の半導体装置。 - 前記金属細線は、金から成ることを特徴とする請求項5記載の半導体装置。
- アイランドと、前記アイランドから連続する吊りリードと、前記アイランドの近傍に一端が配置されて他端が外部に向かって延在する接続リードと、前記吊りリードの上面および前記接続リードの上面に貼着される支持テープとを備え、後の工程にて半導体素子が電気的に接続される領域よりも外側の前記接続リードの上面に前記支持テープが貼着されたリードフレームを用意する工程と、
前記アイランドの上面に半導体素子を固着すると共に、前記半導体素子の上面に設けられた電極と、前記支持テープが貼着された箇所よりも内側の前記接続リードの一端付近の上面とを、金属細線を経由して接続する工程と、
前記アイランド、前記接続リード、前記吊りリード、前記半導体素子、前記金属細線および前記支持テープが被覆されるように封止樹脂を形成する工程と、
を備えたことを特徴とする半導体装置の製造方法。 - 前記支持テープは、前記封止樹脂に被覆された状態で残存することを特徴とする請求項7記載の半導体装置の製造方法。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170026204A (ko) | 2015-08-28 | 2017-03-08 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06268142A (ja) * | 1993-03-16 | 1994-09-22 | Fujitsu Ltd | 半導体装置 |
JP2004228264A (ja) * | 2003-01-22 | 2004-08-12 | Renesas Technology Corp | リードフレーム及びそれを用いた半導体装置並びに半導体装置の製造方法 |
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- 2009-05-29 JP JP2009130653A patent/JP2010278308A/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06268142A (ja) * | 1993-03-16 | 1994-09-22 | Fujitsu Ltd | 半導体装置 |
JP2004228264A (ja) * | 2003-01-22 | 2004-08-12 | Renesas Technology Corp | リードフレーム及びそれを用いた半導体装置並びに半導体装置の製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170026204A (ko) | 2015-08-28 | 2017-03-08 | 르네사스 일렉트로닉스 가부시키가이샤 | 반도체 장치 |
US9805981B2 (en) | 2015-08-28 | 2017-10-31 | Renesas Electronics Corporation | Semiconductor device |
US10020225B2 (en) | 2015-08-28 | 2018-07-10 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
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