CN104103534A - 半导体器件制造方法和半导体器件 - Google Patents
半导体器件制造方法和半导体器件 Download PDFInfo
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- CN104103534A CN104103534A CN201410131172.2A CN201410131172A CN104103534A CN 104103534 A CN104103534 A CN 104103534A CN 201410131172 A CN201410131172 A CN 201410131172A CN 104103534 A CN104103534 A CN 104103534A
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- wire
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000011347 resin Substances 0.000 claims abstract description 51
- 229920005989 resin Polymers 0.000 claims abstract description 51
- 238000007789 sealing Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000008878 coupling Effects 0.000 claims description 20
- 238000010168 coupling process Methods 0.000 claims description 20
- 238000005859 coupling reaction Methods 0.000 claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 13
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 239000000725 suspension Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 19
- 239000004020 conductor Substances 0.000 description 12
- 238000005452 bending Methods 0.000 description 9
- 230000000875 corresponding effect Effects 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 230000003321 amplification Effects 0.000 description 6
- 238000009429 electrical wiring Methods 0.000 description 6
- 238000003199 nucleic acid amplification method Methods 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 238000010422 painting Methods 0.000 description 4
- 230000002459 sustained effect Effects 0.000 description 4
- 241000272168 Laridae Species 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 241000218202 Coptis Species 0.000 description 2
- 235000002991 Coptis groenlandica Nutrition 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012939 laminating adhesive Substances 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L2224/29001—Core members of the layer connector
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- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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Abstract
本发明涉及一种半导体器件和半导体器件的制造方法,其中在QFP即四方扁平封装组装期间将越过汇流条的并耦合到内引线的导线设定在与处于低线弧高度的第二导线以及处于高线弧高度的第三导线不同的线弧高度,并且还安装得比第二导线和第三导线更靠近标准悬空引线。导线的线弧高度相比在树脂密封工艺中的树脂流动的方向逐渐变高,使得可以减小导线偏移并且可以提高QFP组件的可靠性。
Description
相关申请的交叉参考
2013年4月2日提交的日本专利申请No.2013-076787的公开,包括说明书、附图和摘要,其全部作为参考并入在本文中。
技术领域
本发明涉及半导体器件的制造技术和半导体器件,并且例如具体涉及可应用于例如包含汇流条(共用引线)的半导体器件的技术。
背景技术
在日本未审查专利申请公布No.2010-186831中公开了一种用于以下结构的技术,在该结构中:第一汇流条和第二汇流条分别安装在被安装于外周部的引线群和安装半导体芯片的床部之间;并且第一汇流条被安装在与床部相同的高度,第二汇流条被安装在与内引线部相同的高度,并且导线以不同的高度耦合到每个汇流条和内引线部。
在日本未审查专利申请公布No.Hei9(1997)-266223中公开了一种用于以下结构的技术,在该结构中:长导线的线弧高度(loop height)处于不同水平,并且线弧高度从半导体芯片的中心向外围在水平面方面是不同的。
发明内容
越来越需要使半导体器件(封装)的尺寸更小。要求减少端子(外端子,外引线)的数量,以实现更小的尺寸。实现更少端子的一项措施是采用公知的技术,其中接地部与管芯垫绑定在一起并进行导线接合(接地接合),并且对于电源部使用具有在封装内结合在一起的引线端子的汇流条。通过这种方式可以减少端子的数量。
然而,在利用接地接合和汇流条的技术中,通过将接地部和电源部绑定在一起进行多次(多个水平面)导线接合,并且由于树脂密封期间的树脂压力导致导线偏移(导线偏差与导线跨度的比,其施加应力,导致接合点的破裂或脆化)不再是均匀的。因此容易产生电布线短路,使得提供稳定的制造技术是必要的。
用于减小电布线短路的一种已知的技术是将包含结合的引线端子的汇流条相比内引线更多朝向管芯垫一侧延长,并在比内引线的末端的上表面低的位置安装汇流条。该技术能够确保不同长度的导线之间的间隙并防止电布线短路。
然而,在该技术中,在形成引线框期间将汇流条加工成弯曲的形状,以使汇流条的高度在比内引线的末端低的位置。然而在汇流条的外围上需要用于安装在汇流条中形成弯曲的金属模具的空间,这要求缩短环绕汇流条的内引线,或缩短朝向封装的外周部的相邻的内引线。
因此,出现了问题:越过汇流条的接合导线的长度变长,并且这种长度长的导线在树脂密封期间会导致大的导线偏移,从而增加了发生电布线短路的几率。
实现本说明书中描述的实施例的目的是提供能够提高半导体器件组装的可靠性的技术。
通过这些说明书和附图中的描述,其他新颖的特征和其他观点将变得显而易见。
根据本发明的一个方面,半导体器件的制造方法包括:通过导线电耦合半导体芯片的引线和电极垫的工艺,其中,通过第一导线耦合电极垫和第一引线,通过第二导线耦合电极垫和第二引线中的任意一个,并且通过第三导线以比第二导线高的线弧高度耦合电极垫和其他第二引线的任何一个。此外,在上述半导体器件的制造方法中,第二导线安装得比第三导线更靠近于在多个悬空引线当中与用来提供树脂的门的位置对应的标准悬空引线。
根据本发明的这一方面,可以提高半导体器件组装的可靠性。
附图说明
图1是示出本实施例的半导体器件的结构的实例的平面图;
图2是示出在通过密封体(密封树脂)之后图1中的半导体器件的结构的平面图;
图3是示出沿着图2中所示的A-A线划分开的结构的截面图;
图4是示出沿着图2中所示的B-B线划分开的结构的截面图;
图5是示出图1中所示的半导体结构中的布线状态的实例的局部放大平面图;
图6是示出沿着图5中所示的A-A线划分开的结构的局部放大截面图;
图7是示出图1中所示的半导体器件的组装中使用的引线框的结构的实例的局部平面图;
图8是示出放大图7中所示的C部分的局部放大平面图;
图9是示出在组装图1中所示的半导体器件期间管芯接合之后的结构的实例的局部平面图;
图10是示出在组装图1中所示的半导体器件期间导线接合之后的结构的实例的局部平面图;
图11是示出沿着图10中所示的A-A线划分开的结构的局部截面图;
图12是示出沿着图10中所示的B-B线划分开的结构的局部截面图;
图13是示出在图1中所示的半导体器件组装中的树脂模塑期间的结构的实例的局部截面图;
图14是示出在图1中所示的半导体器件组装中的树脂模塑后的结构的实例的局部截面图;
图15是示出在图1中所示的半导体器件组装中的切割和模塑期间的结构的实例的局部截面图;
图16是示出适用实施例的半导体器件的结构的截面图。
具体实施方式
在下面的实施例中,相同或相似部分的描述通常不再重复,除非有必要。
而且,当在以下实施例中有必要为了方便起见,给出了描述,同时分成多个部分或实施例,然而除非另有说明,否则这些部分不是相互无关的,并且一个部分可以是另一个的一部分,或者改写、详细说明和补充说明的全部可以相关。
而且,在以下实施例中,在描述要素(包括件数、数值、量、范围等)的数量时,除非明确说明,并且除了显然的和固有限制在指定数量的情况,否则不会具体限于指定的数量,并且指定数量以上的数量或以下的数量是可以接受的。
不用说,在下面的实施例中,除非另有特别指定和这里清晰地固有要求,结构要素(包括要素步骤等)不总是必需的。
而且在下面的实施例中不必说,当用短语“由A组成”、“由A构成”、“包含A”、“包括A”表达结构要素时,该描述不排除其他要素,除了该描述特别限于这些要素的情况之外。当在下面的描述中表达结构要素等的形状和位置关系等时,包括基本接近或类似这些形状的其他要素,除了另外清楚指定的情况和清楚根本上与此相反的情况。这种情形还适用于上面提到的数量和范围等。
参照附图在下文中描述这些实施例。在描述实施例的所有附图中,具有相同功能的部件被赋予了相同标号,并且省略重复的说明。而且,为了使附图更容易被理解,即使对于平面图,在某些情况下也加入了阴影。
(实施例)图1是示出本实施例的半导体器件的结构实例的平面图;图2是示出在通过密封体之后图1中半导体器件的结构的平面图;图3是示出沿着图2中所示的A-A线划分开的结构的截面图;图4是示出沿着图2中所示的B-B线划分开的结构的截面图;图5是示出图1中所示的半导体结构中的布线状态的实例的局部放大平面图;图6是示出沿着图5中所示的A-A线划分开的结构的局部放大截面图。
图1中所示的本实施例的半导体器件是树脂密封型的,而且是多引脚半导体封装(multi-pinning semiconductor package)。这里,作为实例描述了一种QFP(四方扁平封装)5,其具有在四个方向上分别从由树脂材料形成的树脂体3向外伸出的多个外引线(部分,电极端子,外部耦合端子)1f,并弯曲形成鸥翼形状。
而且如图3所示,QFP(半导体器件)5包含通过上面安装半导体芯片2的管芯垫1c的下表面(背侧)1cb提高散热效率并且从密封体3暴露出的结构。换句话说,QFP5是高散热型半导体封装。更具体地,QFP5是一种管芯垫1c的下表面1cb从作为密封体3的背侧的安装面3b暴露的结构。
接下来描述在图1至图6中所示的QFP(半导体器件)5的结构。
QFP5包含:管芯垫(岛,支撑片)1c,其包含上表面(芯片安装侧)1ca和在与该上表面1ca相反的一侧的下表面1cb;和安装在管芯垫1c的外周的多个内引线(第一引线,电极)1a,和安装在管芯垫1c的外周而且比各个多个内引线短的内引线(第二引线,电极)1b。QFP5进一步包含安装在管芯垫1c的外周的并且从平面图中看还安装在管芯垫1c和多个内引线1b之间的汇流条(共用引线,共用电极,电极)1d。
如图2所示,管芯垫1c(也称为芯片安装部或载带)被悬空引线1e支撑在拐角上。换句话说,在QFP5上,管芯垫1c由四个悬空引线1e支撑。用来从密封体3的安装面3b暴露出管芯垫1c的弯曲部1eb形成在每个悬空引线1e上。通过这种方式,沿着管芯垫1c的高度方向的位置变为低位置(进行载带下降处理),并且如图3所示从密封体3暴露出下表面1cb。
内引线1a、1b或汇流条1d内安装在密封体3中;并且多个外引线1f形成为具有这些内引线1a、1b或汇流条1d的单片,分别从密封体3的四个侧表面3c伸出,作为外部耦合端子。这些多个外端子1f还弯曲形成为鸥翼形状。
QFP5进一步包含半导体芯片2,半导体芯片2包括:主表面2a、形成在主表面2a上面的多个电极垫(电极)2c,和在与主表面2a相反的一侧的背表面2b。该半导体芯片2安装在管芯垫1c的上表面1ca上面。
QFP5进一步包括:分别电耦合半导体芯片2的多个电极垫2c和多个内引线1a、1b和汇流条1d的多个导线(导体)4,以及密封管芯垫1c、汇流条1d、半导体芯片2和多个导线4的一部分的密封体3。
例如,该半导体芯片2由硅形成,多个半导体元件形成在主表面2a上,并且多个半导体元件包括主表面2a一侧的集成电路。如图5所示,半导体芯片2的平面形状是矩形,并且多个电极垫2c沿着半导体芯片2的主表面2a的一侧安装。
在这里进一步详细描述每个构件时,如图3所示,管芯垫1c是板状构件,并包括上表面1ca和在与上表面1ca相反的一侧的下表面1cb。例如,半导体芯片2通过诸如作为导电粘接材料的Ag膏的管芯接合材料(层压粘合剂、管芯接合膜、DAF(管芯附接膜))6接合在该管芯垫1c的上表面1ca上面。如图3和图4所示的管芯垫1c的外尺寸(上表面1ca的尺寸)比半导体芯片2的外尺寸(主表面2a或背表面2b的尺寸)大。换句话说,本实施例的QFP5是大载带结构。
以这种方式,通过使用利用上表面1ca(或下表面1cb)具有比半导体芯片2宽的表面面积的管芯垫1c的大载带结构,可以增强管芯垫1c的散热效果,并且可以提高QEP5的散热效率。
该QFP5进一步包括用作共用(共同利用的)引线的汇流条1d。汇流条1d,例如,将电源导线4汇总成在封装内具有多个耦合的一个引线,用于减少外部端子(外引线1f)的数量,并以这种方式减少了外部端子的数量。其他目的是用于半导体器件的多引脚或小型化。
通过管芯垫1c上的导线管芯接合(接地接合)共同收集接地(GND)导线4用于减少外部端子(外引线1f)的数量,与汇流条1d相同。换句话说,QFP5是大载带结构,并因此是允许导线4与管芯垫1c耦合的结构。
关于本实施例的QFP5,如图2所示汇流条1d是一端结合到外引线1f且另一端结合到另一个外引线1f的形状。此外,如从平面图看到的,汇流条1d的管芯垫1c一侧的端部的位置是与管芯垫1c的边缘上多个内引线1a位置近似整齐排列(arrayed)的位置。
如从平面图看到的,多个内引线1b的每个安装在由汇流条1d围住的区域内。因此多个内引线1b的各个长度(从密封体3的外围位置到管芯垫1c侧的末端的长度。)比多个内引线1a的各个长度短。
换句话说,在如图5所示的本实施例的QFP5中,正如平面图看到的那样,耦合了汇流条1d的导线4的引线部(电极部)1db被安装在多个内引线1b的末端和管芯垫1c的端部之间,因此通过这种方式将多个内引线1b的每个安装在被汇流条1d围住的区域中。而且,多个内引线1b每个的末端与多个内引线1a的每个末端的位置相比位于向着密封体3的外侧(向着外引线1f)偏离(降低)的位置处。
然而,在由一个汇流条1d围住的汇流条区(共用引线区,公共电极区)1da中,多个内引线1b的管芯垫1c一侧的末端位于整齐排列的位置处,正如从平面图所看到的。
而且如图3所示,汇流条1d和多个内引线1b每个的相应高度在同一高度上。也就是说,在本实施例的QFP5中,在密封体内的位置处没有弯曲形成汇流条1d,使得多个内引线1a的每个、多个内引线1b的每个和多个汇流条1d安装在同一高度上。
在密封体内的位置处没有弯曲形成各自的汇流条1d,使得在图5所示的汇流条区1da中不需要确保来安装用于在汇流条1d中形成弯曲的金属模具的空间。因此,在上述汇流条区1da中,在汇流条1d附近的端部的内引线1b的在管芯垫1c一侧的末端可以安装在正如从平面图上看到的与其他内引线1b的末端整齐排列的位置处。
接下来描述QFP5的导线4。在如图2和图5所示的QFP5上,在多个导线4之间,半导体芯片2的多个电极垫2c和多个内引线(第一引线,电极)1a通过多个第一导线(第一导体)4a电耦合。
半导体芯片2的多个电极垫2c和多个内引线(第二引线,电极)1b电耦合到第二导线(第二导体)4b或第三导线(第三导体)4c中的任何一个。如图3所示,多个第二导线4b和多个第三导线4c的每个都形成为越过汇流条1d。多个第二导线4b的各个线弧高度在此时形成为比多个第三导线4c的各个线弧高度低。
换句话说,有两种类型的线弧高度的导线4,它们是在形成了第二导线4b和第三导线4c的汇流条区1da中的第二导线4b和第三导线4c。
在本实施例的QFP5中,第二导线4b和第三导线4c都没有必要安装在所有汇流条1d中的这些汇流条区1da中,只是汇流条区1da内的多个第三导线4c可以分别耦合到多个内引线1b的每个。在这种情况下,对于汇流条区1da内的导线4(第三导线4c),仅有一种类型的线弧高度。
于是,描述了本实施例的QFP5的任意汇流条1d的汇流条区1da中优选安装两种类型的线弧高度的导线4的要点。
在QFP5中支撑管芯垫1c的四个悬空引线中,有对应图10所示的门12ab的位置的标准悬空引线1ea,门12ab在组装QFP5时的树脂密封期间供应密封树脂(树脂,参见图13)。
因此在树脂密封期间,必须设定导线4的线弧高度,同时使导线相对于从标准悬空引线1ea的附近流动的密封树脂10的流动方向(见图9)偏移。
首先,由于来自在标准悬空引线1ea附近流动的密封树脂10的树脂压力,容易产生导线偏移,使得当在邻近标准悬空引线1ea的汇流条1d附近存在汇流条区1da时,第二导线4b和第三导线4c优选形成为越过与该汇流条区1da相关的汇流条1d,并在不同的线弧高度上形成。
而且,如图5中的空间部P所示,当半导体芯片2的电极垫2c中存在没有耦合到导线4的多个共同安装的电极垫2c时,在比较靠近标准悬空引线1ea的导线阵列中,形成了导线阵列中没有导线4的空间部P。
在这种类型的空间部P中,当密封树脂10在树脂密封期间流动时,没有导线4,使得对密封树脂10的阻力小并且密封树脂10的流速增加。因此,当在该空间部P中的密封树脂10的流动方向8的下游侧之后立即形成高线弧的导线4时,对密封树脂10的阻力增加并且容易产生导线偏移。
因此,当在流向空间部P的下游侧之后在附近(紧接在之后)存在汇流条1d的汇流条区1da时,第二导线4b和第三导线4c优选形成为越过与该汇流条区1da相关的汇流条1d,并且还形成在不同的线弧高度上。
在形成了第二导线4b和第三导线4c的汇流条区1da中,第二导线4b被安装得相比第三导线4c更靠近标准悬空引线1ea。换句话说,在形成了第二导线4b和第三导线4c的汇流条区1da中,相比具有高线弧高度的第三导线4c,具有低线弧高度的第二导线4b被安装得更接近标准悬空引线1ea附近的一侧。
于是,在本实施例的QFP5中,在安装在该汇流条区1da内的多个内引线1b当中,在形成了第二导线4b和第三导线4c的汇流条区1da中,第二导线4b被电耦合到安装在标准悬空引线1ea附近的端部的内引线1b。
也就是说,在形成了第二导线4b和第三导线4c的汇流条区1da中,具有低线弧高度的第二导线4b被安装在图5中的标准悬空引线1ea附近的端部,因此在汇流条区1da中,安装多个导线4使得线弧高度从标准悬空引线1ea逐渐变高。
在汇流条区1da中,可以从标准悬空引线1ea附近的边缘连续地安装具有低线弧高度的多个第二导线4b。
在该汇流条区1da中,在第二导线4b的标准悬空引线1ea一侧,如图6所示在第二导线4b附近安装具有比第二导线4b低的线弧高度的第四导线4d(第四导体);并且如图5所示该第四导线4d电耦合到汇流条1d。
另外,在汇流条区1da中的第四导线4d的标准悬空引线1ea一侧,存在没有耦合到任何导线4的半导体芯片2的多个连续的电极垫2c。换句话说,形成没有耦合到任何导线4的多个连续的电极垫2c,用于形成如图5所示的空间部P,并且耦合到汇流条1d的第四导线4d还被安装在空间部P的下游侧(离开标准悬空引线1ea的一侧)。而且,在该第四导线4d的下游侧,具有比第四导线4d高的线弧高度的三个第二导线4b越过各自的汇流条1d并耦合到内引线1b。然后,在这三个第二导线4b的下游侧,具有比第二导线4b高的线弧高度的第三导线4c,越过汇流条1d,并耦合到其他内引线1b。
换句话说,形成每个导线4使得导线4的线弧高度紧接在空间部P的下游侧(离开标准悬空引线1ea的一侧)之后,在有空间部P的那一点处逐渐变高。
在如图6所示的QFP5中,具有比第四导线4d低的线弧高度的第五导线(第五导体)4e被电耦合到管芯垫1c。第五导线4e是所谓的接地的接合导线。换句话说,在QFP5中,管芯垫1c在GND(地)电压电位。连接到汇流条1d的汇流条1d和多个第四导线4d例如在电源电压电位。
在QFP5中,在每个导线4的线弧高度当中,第五导线4e最低,并且是其中第五导线4e<第四导线4d=第一导线4a<第二导线4b<第三导线4c的状态。
在本实施例的QFP5中,如2图所示,在每个内引线1a、1b和每个汇流条1d的表面上面,将环形带材7附接到用于每个导线4的耦合点的外侧上的区域上。
该带材7能防止在多个内引线1a、1b或汇流条1d的组装工艺中的摆动(flapping),并且附接带材7降低了内引线1a、1b和汇流条1d在组装工艺中的变形(翘曲)。
多个导线4(第一导线4a、第二导线4b、第三导线4c、第四导线4d和第五导线4e)例如是直径为约18至20μm的窄导线。用作主要成分的材料优选是铜,但是用作为主要成分的材料不限于铜。
而且,管芯垫1c、内引线1a、1b、外引线1f、汇流条1d和悬空引线1e是包括主要成分是铜的合金,但并不限于这种材料。
例如,密封体3由环氧型热固性树脂制成。
在本实施例的QFP5中,汇流条1d没有经受弯曲成形,因此汇流条1d和内引线1a、1b是同一高度。换句话说,在相对于各汇流条1d的密封体内的位置没有弯曲成形,使得在汇流条区1da中不需要确保用于安装在汇流条1d中形成弯曲的金属模具的空间。
在该汇流条区1da中,安装在内引线1b阵列当中的汇流条1d附近的端部的内引线1b的管芯垫1c侧的末端,可以以这种方式安装在与其他内引线1b的末端对准的位置,正如从平面图看到的那样,在密封体3的外周方向上没有偏差(偏移)。
换句话说,在安装在汇流条1d附近的端部的内引线1b的长度,可以制作成与其他内引线1b相同的长度,而无需缩短。
因此,没有缩短安装在汇流条区1da中的端部的内引线1b,所以耦合到该内引线1b的导线4(第二导线4b)的长度可以制作得较短。
可以以这种方式减小在该导线4的树脂密封工艺中发生的导线偏移。
而且,耦合至安装在汇流条区1da的端部的内引线1b的导线4(第二导线4b)的长度短,使得可以减少导线4的布线成本,并且可以降低QFP5的成本。
另外,对汇流条1d弯曲成形不需要金属模塑,因此可以降低QFP5的制造成本。
多条导线4(第一导线4a、第二导线4b、第三导线4c、第四导线4d和第五导线4e)是由主要成分为铜(铜线),并且铜(Cu)线比金(Au)线硬,使得可以提高导线4的强度,并且可以限制树脂密封工艺中的导线偏移。
相比金线,铜丝的成本也较低,使得可以实现低成本的QFP5。
接下来描述用于本实施例的半导体器件(QFP5)的组装过程。
图7是示出在图1中所示的半导体器件的组装中使用的引线框结构的实例的局部平面图。图8是示出放大图7中所示的C截面的局部放大平面图。图9是示出在组装图1中所示的半导体器件期间在管芯接合之后的结构的实例的局部平面图。图10是示出在组装图1中所示的半导体器件期间在管芯接合之后的结构的实例的局部平面图。图11是示出沿着图10中所示的A-A线划分开的结构的局部截面图。图12是示出沿着图10中所示的B-B线划分开的结构的局部截面图。此外,图13是示出在组装图1中所示的半导体器件时的树脂模塑期间的结构的实例的局部截面图。图14是示出在组装图1中所示的半导体器件时的树脂模塑之后的结构的实例的局部截面图。图15是示出在组装图1中所示的半导体器件时的切割和模塑期间的结构的实例的局部截面图。
首先在图7中制备引线框1。引线框1是由多个器件区1g以矩阵形成的多个条板材料。每个器件区1g由框架1h围住。在相邻的器件区1g之间形成狭缝孔1i。当在组装期间应力施加到引线框1上时,狭缝孔1i用作缓解应力的形状。
例如,引线框1包括主要成分是铜的合金材料,但引线框不限于这种材料。
在图8所示的每个器件区1g中,管芯垫(岛、支撑片)1c包含上表面(芯片安装表面)1ca和在图3中的相反侧的下表面(背表面)1cb,四个悬空引线1e支撑管芯垫1c,多个内引线(第一引线,电极)1a安装在管芯垫1c的外周,多个内引线(第二引线,电极)1b的长度分别比多个内引线1a短。
而且,正如从平面图看到的那样,包含引线部(电极部)的多个汇流条(共用引线、共用电极、电极)1db安装在管芯垫1c和多个内引线1b之间的区域上面。
在如图2所示的一片中,形成外引线1f至每个内引线1a、1b和每个汇流条1d。
各内引线1a、1b的末端的表面和汇流条1d的导线部1db的表面涂覆有银(Ag)涂层,以提供与导线(导体)4的令人满意的耦合。
在每个悬空引线1e中形成弯曲部1eb,并且在比内引线1a、1b和汇流条1d低的位置安装管芯垫1c。换句话说,对引线框1执行载带下降工艺。
当在管芯接合工艺中安装半导体芯片2时,在每个管芯垫1c的上表面上面形成用作位置地标的微凹部1cc。在管芯垫1c上面安装半导体芯片2使得不遮盖该微凹部1cc。
在微凹部1cc的外侧上形成板涂覆部1cd。对该板涂覆部1cd实施接地芯片结合。因此,在板涂覆部1cd上涂覆例如银(Ag)镀层。
在相邻的悬空引线1e之间分别形成多个内引线1a和内引线1b与汇流条1d。多个内引线1b安装在汇流条区(共用引线树脂、公共电极区)1da内,其是被汇流条1d包围的区域。因此多个内引线1b的各个长度比多个内引线1a的每一个短。
多个内引线1a的各个末端位置与耦合了汇流条区1da的导线4的引线部1db的位置相同,并且其末端如从平面图看到地整齐排列。
在汇流条1d上的位置没有弯曲形成,因此在汇流条区1da中没有必要确保用于安装金属模具以形成在汇流条1d形成弯曲的空间。
因此,在汇流条区1da中,因此安装在内引线1b阵列当中的汇流条1d附近的端部的内引线1b的管芯垫1c侧的末端可以以这种方式安装在如从平面图看到地与其他内引线1b的末端整齐排列的位置处,而在器件区1g的外周方向上没有偏差(偏移)。换句话说,汇流条区1da内的多个内引线1b的末端都被安装在如从平面图看到的整齐排列位置。
在本实施例的引线框1中,在汇流条1d上没有形成弯曲,因此多个内引线1a、多个内引线1b和多个汇流条1d安装在同一高度上。
而且,在每个器件区1g上面,将环形带材7附接到多个内引线1a、1b和汇流条1d的表面上。以这种方式,带材7能防止在用于多个内引线1a、1b或汇流条1d的组装过程中的摆动,并且也减小了由于组装过程中的摆动而出现的内引线1a、1b或汇流条1d的变形(翘曲)。
如图9所示,接下来执行管芯接合。这里,如图3所示,在管芯垫1c的上表面1ca上面安装半导体芯片2,半导体芯片2包括主表面2a、形成在主表面2a的周边2c上面的多个电极垫(电极)和在主表面2a相反侧上的后表面2b。
此时在管芯垫1c的上表面上1ca上面涂覆诸如图3所示的Ag膏的芯片接合材料(粘接材料、层压粘合剂、芯片接合薄膜、DAF)6。在涂覆后,将例如由图中未示出的筒夹拾取并传送的半导体芯片2安装在管芯垫1c的上表面上1ca上面,并且如图9所示,在半导体芯片2的主表面2a面朝上的状态下借助管芯焊接材料6附接在管芯垫1c的上表面上1ca上面。
此后,执行如图10所示的导线接合。在该导线接合工艺中,半导体芯片2的多个电极垫2c、管芯垫1c、汇流条1d、多个内引线(第一引线、电极)1a和多个内引线(第二引线、电极)1b中的每个借助多条导线4电耦合。
在该导线接合工艺中,按照导线4的多个类型的线弧高度当中的低线弧高度的顺序执行导线接合。
在本实施例的QFP5中,导线接合到管芯垫1c的接地结合具有最低的线弧高度,因此首先如图11和图12所示,多条第五导线(第五导体)4e电耦合(执行接地结合)到管芯垫1c。在这种情况下,将第五导线4e耦合到8图中所示的管芯垫1c的上表面1ca的板涂覆部1cd。
此后,执行导线接合到内引线1a和用作共用引线的汇流条1d。换句话说,多个内引线1a和多个汇流条1d中的每个是相同的高度,并且如从平面图看到的,多个内引线1a的每个末端的位置和汇流条1d的各自的多个引线部1db的位置近似整齐排列,使得在同一工艺中执行导线接合到内引线1a和汇流条1d。
半导体芯片2的多个电极垫2c和多个内引线1a的每个由多个第一导线(第一导体)4a电耦合,如图12所示。此时,通过将多个第一导线4a的线弧高度设定得比多个第五导线4e的各个线弧高度高来执行导线接合。
此外,由多个第四导线(第四导线)4d电耦合半导体芯片2的多个电极垫2c和多个汇流条1d的引线部1db,如图11所示。此时,导线接合是通过将多个第四导线4d的线弧高度设定成与多个第一导线4a相同的各线弧高度来执行的。
在引线框1中支撑管芯垫1c的四个悬空引线1e中,有对应于图10中的门12ab的位置的标准悬空引线1ea,门12ab用于在树脂密封工艺中供应密封体(树脂,参见图13)。
在引线框1中,当由一个汇流条1d包围的区域设定为汇流条区(共用引线区、共用电极区)1da时,因此形成第四导线4d使得邻近第二导线(第二导体)4b并且使得第四导线4d的线弧高度比该汇流条区1da中的第二导线4b低。在这种情况下,第四导线4d耦合到汇流条1d,使得第四导线4d安装在相比第二导线4b更靠近标准悬空引线1ea。
然而,在该阶段仍然没有第二导线4b的导线接合,使得用于导线接合的多个第四导线4d当中的至少任何一个都耦合到每个汇流条1d的引线部1db的标准悬空引线1ea一侧的端部,并且也在与第一导线4a相同的线弧高度处。
而且在如图10中的空间部P所示的半导体芯片2的多个电极垫2c当中,在该位置有连续的多个电极垫2c没有耦合到任何导线4;在汇流条区1da中,这些多个电极垫2c没有耦合到这些导线4,将第四导线4d耦合到汇流条1d以安装在第四导线4d的至少标准悬空导线1ea一侧。
在标准悬空引线1ea附近的汇流条1d中,即使在耦合标准悬空引线1ea的管芯垫1c的拐角附近,第四导线4d也以与第一导线4a相同的线弧高度耦合到该汇流条1d的引线部1db的标准悬空引线1ea的端部。
半导体芯片2的多个电极垫2c之后通过多个第二导线4b电耦合到安装在汇流条区1da中的多个内引线1b的任何一个。在这种情况下,形成多个第二导线4b的每个越过汇流条1d。而且,第二导线4b是导线接合,使得如图11所示的线弧高度比第五导线4e、第一导线4a、第四导线4d的各线弧高度更高。
此外,如图10所示,汇流条区1da中的第二导线4b在距离标准悬空引线1ea侧的最远端位置电耦合到内引线1b。
在汇流条区1da中的第二导线4b的标准悬空引线1ea一侧具有比第二导线4b低的线弧高度的第四导线4d,可以在靠近第二导线4b安装的状态下以这种方式耦合到汇流条1d。
换句话说,在邻接第二导线4b、在比第二导线4b低的线弧高度并且相比第二导线4b更靠近标准悬空引线1ea的状态下,第四导线4d耦合到汇流条区1da中的汇流条1d。
而且,将没有耦合到任何导线4的半导体芯片2的那些多个电极垫2c连续地安装在汇流条区1da中的第四导线4d的标准悬空引线1ea一侧,因此在如这里描述形成的导线阵列内存在空间部P。
第二导线4b不必用在每个汇流条区1da中,用于导线接合第二导线4b的汇流条区1da是包括在图10的空间部P中所示的多个电极垫2c当中没有耦合导线4的连续多个电极垫2c的位置的汇流条区1da,或在标准悬空引线1ea附近的汇流条区1da。
第二导线4b可以从安装在内引线1b阵列当中的端部处的内引线1b导线接合到连续排列的内引线1b的每一个。
之后,半导体芯片2的多个电极垫2c和内引线1b的其他引线的任何一个可以形成为通过第三导线(第三导体)4c越过汇流条1d,并且在比第二导线4b高的线弧高度还电耦合到内引线1b。
换句话说,在各个多个汇流条区1da中,没有耦合到第二导线4b的剩余的多个内引线(其他引线)1b通过多个第三导线4c被耦合到半导体芯片2的对应的多个电极垫2c。在这种情况下,第三导线4c越过汇流条1d,并且还在比第二导线4b高的线弧高度电耦合到多个内引线(其他引线)1b。
另外,在耦合了第二导线4b的多个汇流条区1da中,形成第三导线4c,使得第二导线4b被定位为相比第三导线4c更靠近标准悬空引线1ea。
每个导线4以这样的方式达到了以下状态:分别电耦合至半导体芯片2的多个电极垫2c、和对应于半导体芯片2的多个电极垫2c的多个内引线1a、1b和汇流条1d。
换句话说,本实施例的导线接合,包括实施为使得越过汇流条1d的导线4的线弧高度是用于第二导线4b和第三导线4c的两种类型的线弧高度的导线接合;并且包括其中形成使用这两种类型的线弧高度的第二导线4b和第三导线4c的汇流条区1da。
然后,在形成了第二导线4b和第三导线4c的汇流条区1da中,安装每个导线4,使得由于第二导线4b安装在比标准悬空引线1ea的端部低的线弧高度,导线4的线弧高度从标准悬空引线1ea一侧逐渐变高。
可以设定标准悬空引线1ea,使得另一邻接的悬空引线1e(定位在图13所示的柱塞12c一侧的两个悬空引线1e当中的任何一个)用作标准悬空引线1ea。
因此,无论哪一个悬空引线1e被设定用于标准悬空引线1ea,即使在标准悬空引线1ea任何一个附近的汇流条区1da中,第二导线4b和第三导线4c也都可以形成在如上所述的两种类型的线弧高度处,使得实施对于导线偏移的对策。
每个导线4优选是其主要成分为例如铜的材料。铜线相比金(Au)线更硬,使得利用铜(Cu)线提升了导线4的强度并且限制了树脂密封工艺中的导线偏移。
铜丝相比金线成本也较低,使得可以降低QFP5组件的成本。
在导线接合之后,如图13所示执行该树脂模塑(树脂密封)。这里,密封树脂10密封内引线1a、1b、汇流条1d、半导体芯片2和多个导线4,使得图14中的外引线(部、电极端子、外部电极端子)1f从密封体3伸出,该外引线1f作为一片分别连接到图10中所示的多个内引线1a、1b和汇流条1d。
在如图13所示的该树脂模塑中,首先制备包括上模具12a和下模具12b对的树脂模塑模具(金属模具)12,在由各自的金属模塑腔12ba、12ba形成的空间部11中安装引线框1,然后夹紧上模具12a和下模具12b。
通过柱塞12c挤压出加热的密封树脂10,并且由流道12d和门12ab将密封树脂10供应到由腔12ba、12ba形成的空间部11。
图13中的密封树脂10是以这种方式从图10中所示的门12ab浇注到引线框1的每个器件区1g。密封树脂10沿着流动方向8流入到每个器件区1g。
将具有低线弧高度的第二导线4b安装在标准悬空导线1ea附近的端部,在对应于门12ab位置的标准悬空引线1ea附近的汇流条区1da中,以及在其中没有耦合到导线4的电极垫2c被集体安装的空间部P附近的汇流条区1da中。安装每个导线层4使得导线4的导线线弧高度从标准悬空引线1ea一侧逐渐更高。
换句话说,在上述的汇流条区1da中,导线4的线弧高度相对于上述密封树脂10的流动方向8逐渐变高,使由于树脂流动而对该导线4的阻力得到缓解且因而可以减少导线偏移的发生。
正如从导线一侧看到的,从密封树脂10的流动维持的压力(负载)开始小且被减轻到逐渐变大,使得可以减小在树脂模塑期间发生的导线偏移。
因此,可以防止由于导线偏移而引起的电布线短路的发生,并且在QFP5组装工艺中提高了可靠性。
执行越过汇流条的导线接合允许在高的线弧高度形成导线4,使得对于容易发生导线偏移的第二导线4b和第三导线4c,通过设置不同的线弧高度改变线弧高度,即使例如在发生了导线偏移的情况下,也允许限制电布线短路的发生。
通过接下来结束将密封树脂10供应到腔12aa、12ba的空间部11并且执行烘焙处理等,形成图14中所示的密封体3,并且现在完成了树脂模塑。管芯垫1c的下表面1cb从密封体3的安装面3b暴露出。
在完成树脂模塑后,然后对密封体3的表面3a进行所希望的标记。
然后进行切割和模塑。从如图15所示的引线框1切断从密封体3暴露出的各自的多个外引线1f。在切断之后,使多个外引线1f的每个弯曲形成为鸥翼形状。
上述处理完成了QFP5的组装。
基于本发明的实施例上面具体详细描述了由发明人提供的发明。然而本发明不会受到该实施例的限制,并且改变和适应的所有方式都没有脱离本发明的精神和范围是允许的。
例如,在本实施例中,鉴于对于利用载带曝光型结构从密封体3的安装面3b暴露管芯垫1c的下表面1cb的情况需要散热效果,来说明半导体器件(QFP5)。然而,半导体器件可以利用图16中的变形所示的载带嵌入型。
换句话说,图16中所示的半导体器件是该实施例的修改的半导体器件,并且是管芯垫1c嵌入密封体3中的载带嵌入式QFP(四方扁平封装)。
该修改的载带嵌入式的QFP13也能够呈现出与上述实施例的QFP5相同的效果。
Claims (10)
1.一种半导体器件的制造方法,包括以下步骤:
(a)制备引线框,所述引线框包括:包含芯片安装表面的管芯垫、支撑所述管芯垫的多个悬空引线、安装在所述管芯垫外围处的多个第一引线、长度比各个第一引线短的多个第二引线、和从平面图看时安装在所述管芯垫和所述第二引线之间的共用引线;
(b)在所述管芯垫的所述芯片安装表面上面安装主表面上面形成有多个电极垫的半导体芯片;
(c)通过多个导线将所述半导体芯片的所述电极垫、所述共用引线、以及所述第一引线和所述第二引线中的每一个电耦合;
(d)利用树脂密封所述共用引线、所述半导体芯片和所述导线,使得从密封体暴露出所述第一引线和所述第二引线以及所述共用引线中的每一个的一部分;以及
(e)从所述引线框切断从所述密封体暴露出的多个外引线;
其中,在所述步骤(c)中:
所述导线中的第一导线将所述电极垫和所述第一引线电耦合,
所述导线中的第二导线越过所述共用引线,并且将所述电极垫和所述第二引线中的任何一个引线电耦合,
所述导线中的第三导线越过所述共用引线,并且还以比所述第二导线高的线弧高度将所述电极垫和其他第二引线中的任何一个电耦合,并且
相对于所述悬空引线当中的、与在树脂密封期间用于供应树脂的门匹配的位置处的标准悬空引线,在与所述共用引线对应的共用引线区中所述第二导线被安装为比所述第三导线更近。
2.根据权利要求1的半导体器件的制造方法,
其中,在所述步骤(c)中:
在所述共用引线区中在所述第二导线的所述标准悬空引线一侧,具有比所述第二导线低的线弧高度的第四导线被安装在所述第二导线附近,以便电耦合到所述共用引线。
3.根据权利要求2的半导体器件的制造方法,
其中,在所述步骤(c)中:
所述半导体芯片的没有耦合导线的电极垫被安装在所述共用引线区中的所述第四导线的所述标准悬空引线一侧。
4.根据权利要求3的半导体器件的制造方法,
其中,在所述步骤(c)中:
所述第二导线被电耦合到所述共用引线区中的最靠近所述标准悬空引线的端部的位置处的所述第二引线。
5.根据权利要求1的半导体器件的制造方法,
其中,在所述步骤(c)中:
第四导线被安装为在所述共用引线区中邻近所述第二导线,并且还通过将所述第四导线的线弧高度设定为比所述第二导线低而被安装为比所述第二导线更靠近所述标准悬空引线,并且所述第四导线电耦合到所述共用引线。
6.根据权利要求2的半导体器件的制造方法,
其中,在所述步骤(c)中:
具有比所述第四导线低的线弧高度的第五导线被电耦合到所述管芯垫。
7.根据权利要求1的半导体器件的制造方法,
其中,所述导线包括主要成分为铜的材料。
8.一种半导体器件,包括:
管芯垫,所述管芯垫包括芯片安装表面;
多个第一引线,所述第一引线被安装在所述管芯垫的外围;
多个第二引线,所述第二引线的长度比各个第一引线短;
共用引线,所述共用引线从平面图上看时被安装在所述管芯垫和所述第二引线之间;
半导体芯片,所述半导体芯片被安装在所述管芯垫的所述芯片安装表面上面,并且多个电极垫被形成在所述芯片的所述主表面上面;
多个第一导线,所述第一导线将所述半导体芯片的所述电极垫和所述第一引线电耦合;
多个第二导线或第三导线,所述第二导线或所述第三导线将所述半导体芯片的所述电极垫和所述第二引线电耦合;
密封体,所述密封体密封所述管芯垫的一部分、所述共用引线、所述半导体芯片以及所述第一导线、所述第二导线和所述第三导线;和
多个外引线,所述外引线从所述密封体暴露出,
其中,所述第二导线和所述第三导线分别被形成为越过所述共用引线,
其中,所述第二导线的线弧高度比所述第三导线的线弧高度低,并且
其中,所述第二引线中的每一个的所述管芯垫一侧的末端与所述共用引线的高度是相同的。
9.根据权利要求8的半导体器件,
其中,所述第一导线、所述第二导线和所述第三导线包括主要成分为铜的材料。
10.根据权利要求9的半导体器件,
其中,所述管芯垫的背侧在所述密封体的背侧暴露出。
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CN102157485B (zh) * | 2011-03-23 | 2012-10-03 | 南通富士通微电子股份有限公司 | 一种半导体封装框架 |
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US10297534B2 (en) | 2014-12-11 | 2019-05-21 | Stmicroelectronics Pte Ltd | Integrated circuit (IC) package with a solder receiving area and associated methods |
CN105702652B (zh) * | 2014-12-11 | 2019-10-18 | 意法半导体有限公司 | 带有焊料接纳区域的集成电路(ic)封装体及相关联方法 |
US10529652B2 (en) | 2014-12-11 | 2020-01-07 | Stmicroelectronics Pte Ltd | Integrated circuit (IC) package with a solder receiving area and associated methods |
CN110954034A (zh) * | 2019-12-12 | 2020-04-03 | 深圳赛意法微电子有限公司 | 一种半导体器件的导线线弧高度测量方法 |
CN110954034B (zh) * | 2019-12-12 | 2021-06-11 | 深圳赛意法微电子有限公司 | 一种半导体器件的导线线弧高度测量方法 |
CN112435979A (zh) * | 2020-09-30 | 2021-03-02 | 日月光半导体制造股份有限公司 | 引线单元及引线框架 |
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CN104103534B (zh) | 2018-06-22 |
HK1201983A1 (zh) | 2015-09-11 |
JP6164895B2 (ja) | 2017-07-19 |
US20140291826A1 (en) | 2014-10-02 |
JP2014203879A (ja) | 2014-10-27 |
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