JP5798021B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5798021B2 JP5798021B2 JP2011263744A JP2011263744A JP5798021B2 JP 5798021 B2 JP5798021 B2 JP 5798021B2 JP 2011263744 A JP2011263744 A JP 2011263744A JP 2011263744 A JP2011263744 A JP 2011263744A JP 5798021 B2 JP5798021 B2 JP 5798021B2
- Authority
- JP
- Japan
- Prior art keywords
- leads
- lead
- semiconductor device
- sealing body
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
図1は本発明の実施の形態1の半導体装置の構造の一例を示す平面図、図2は図1の半導体装置の構造を封止体を透過して示す平面図、図3は図1の半導体装置の構造の一例を示す裏面図、図4は図1の半導体装置の構造の一例を示す側面図、図5は図2のA−A線に沿って切断した構造の一例を示す断面図である。また、図6は図2のW部の構造を示す拡大部分平面図、図7は図6のC−C線に沿って切断した構造の一例を示す断面図、図8は図6のD−D線に沿って切断した構造の一例を示す断面図、図9は図6のE−E線に沿って切断した構造の一例を示す断面図、図10は図6のF−F線に沿って切断した構造の一例を示す断面図である。
図26は本発明の実施の形態2の半導体装置の構造の一例を封止体を透過して示す平面図である。
1a 表面(主面)
1b 裏面
1c 電極パッド
2 リードフレーム
2a リード
2aa 上面
2ab 下面
2b アウター部
2c,2ca 吊りリード
2d ダイパッド
2da 上面
2db 下面
2e インナー部
2f 外側端面
2g 内側端面
2h,2i 側面
2j 中央リード
2k 先端部
2m 後端部
2n,2p,2q 段差部
2r 迫り出し面
2s デバイス領域
2t 枠部
2u 幅広部
2v ワイヤ接合部
2w 延在方向
3 ワイヤ
4 封止体
4a 側面
4b 下面
4c 一括封止体
5 QFN(半導体装置)
6 ダイボンド材
7 中心線
8 延在方向
9 ブレード
10 ダイシングテープ
11 QFN(半導体装置)
Claims (10)
- ダイパッドと、
前記ダイパッドを支持する複数の吊りリードと、
前記複数の吊りリードの間に配置された複数のリードと、
主面、前記主面に形成された複数の電極パッド、および前記主面とは反対側の裏面を有し、かつ前記ダイパッドの上面に搭載された半導体チップと、
前記半導体チップの前記複数の電極パッドと前記複数のリードとをそれぞれ電気的に接続する複数のワイヤと、
前記複数のリードのそれぞれの下面が露出するように、前記半導体チップおよび前記複数のワイヤを封止する封止体と、
を含み、
前記複数のリードのそれぞれは、前記封止体から露出する前記下面と、前記下面とは反対側の上面と、前記上面と前記下面との間に位置し、かつ、前記ダイパッドと対向する内側端面と、前記内側端面とは反対側に位置し、かつ、前記封止体から露出する外側端面と、前記上面と前記下面との間に位置し、かつ、前記内側端面と前記外側端面との間に位置する第1側面と、前記第1側面とは反対側の第2側面と、を有しており、
さらに、前記複数のリードのそれぞれは、前記複数のリードのそれぞれの延在方向において、前記内側端面側に位置する第1部分と、前記第1部分よりも前記外側端面側に位置する第2部分と、を有しており、
前記第1側面における前記第1部分で、かつ、前記下面よりも前記上面側には、前記第1側面から突出するように第1ひさし部が形成されており、
前記第2側面における前記第2部分で、かつ、前記下面よりも前記上面側には、前記第2側面から突出するように第2ひさし部が形成されており、
前記第1側面における前記第2部分には、前記第1および第2ひさし部は形成されていなく、
前記第2側面における前記第1部分には、前記第1および第2ひさし部は形成されていないことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれの前記内側端面で、かつ、前記下面よりも前記上面側には、前記内側端面から突出するように第3ひさし部が形成されていることを特徴とする半導体装置。 - 請求項2に記載の半導体装置において、
前記第3ひさし部の前記ダイパッド方向への迫り出し量は、前記第1ひさし部の隣り合った前記リード方向への迫り出し量、および前記第2ひさし部の隣り合った前記リード方向への迫り出し量よりそれぞれ大きいことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記封止体の平面形状は、四角形からなり、前記複数のリードは、平面視において、前記封止体の各辺に沿って奇数本ずつ配置され、
前記各辺において、前記奇数本の前記リードにおける中央リードを線対称とした形態になるように、前記複数のリードのそれぞれの前記第1および前記第2ひさし部が形成されていることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記中央リードの第1部分には、平面視で幅広となる幅広部が形成されていることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記第1ひさし部が形成された前記第1側面は、前記ワイヤの延在方向側であることを特徴とする半導体装置。 - 請求項4に記載の半導体装置において、
前記各辺の前記奇数本の前記リードのうち、前記中央に配置される前記リード以外のリードは、それぞれの前記リードの第1部分の平面視の形状が、前記ワイヤの延在方向に沿うように屈曲していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記封止体の平面形状は、四角形からなり、前記複数のリードは、平面視において、前記封止体の各辺に沿って偶数本ずつ配置され、
前記各辺において、前記偶数本の前記リードは、各リードの前記第1および前記第2ひさし部が前記偶数本の前記リードの配列方向に対してそれぞれ同一の向きに形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれは、エッチング加工によって形成されたものであることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれの前記第2側面の前記第2部分に形成された前記第2ひさし部は、前記封止体の内部で終端していることを特徴とする半導体装置。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011263744A JP5798021B2 (ja) | 2011-12-01 | 2011-12-01 | 半導体装置 |
TW101135676A TWI540691B (zh) | 2011-12-01 | 2012-09-27 | Semiconductor device |
CN2012206136162U CN202996818U (zh) | 2011-12-01 | 2012-11-12 | 半导体器件 |
CN201210470646.7A CN103137592B (zh) | 2011-12-01 | 2012-11-12 | 半导体器件 |
KR1020120134989A KR101953393B1 (ko) | 2011-12-01 | 2012-11-27 | 반도체 장치 |
US13/692,286 US8836106B2 (en) | 2011-12-01 | 2012-12-03 | Semiconductor device |
US14/465,379 US9443794B2 (en) | 2011-12-01 | 2014-08-21 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011263744A JP5798021B2 (ja) | 2011-12-01 | 2011-12-01 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013118215A JP2013118215A (ja) | 2013-06-13 |
JP5798021B2 true JP5798021B2 (ja) | 2015-10-21 |
Family
ID=48497205
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011263744A Expired - Fee Related JP5798021B2 (ja) | 2011-12-01 | 2011-12-01 | 半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (2) | US8836106B2 (ja) |
JP (1) | JP5798021B2 (ja) |
KR (1) | KR101953393B1 (ja) |
CN (2) | CN103137592B (ja) |
TW (1) | TWI540691B (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5798021B2 (ja) * | 2011-12-01 | 2015-10-21 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN104347570B (zh) * | 2013-07-26 | 2018-07-20 | 恩智浦美国有限公司 | 无引线型半导体封装及其组装方法 |
JP6825660B2 (ja) * | 2013-07-31 | 2021-02-03 | 日亜化学工業株式会社 | リードフレーム、樹脂付きリードフレーム、樹脂パッケージ、発光装置及び樹脂パッケージの製造方法 |
JP6210818B2 (ja) * | 2013-09-30 | 2017-10-11 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP5908508B2 (ja) | 2014-02-25 | 2016-04-26 | ファナック株式会社 | プリント基板 |
JP6284397B2 (ja) * | 2014-03-10 | 2018-02-28 | エイブリック株式会社 | 半導体装置及びその製造方法 |
EP3316294A4 (en) * | 2015-06-24 | 2019-02-20 | Renesas Electronics Corporation | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE |
JP2017045944A (ja) * | 2015-08-28 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN106935565A (zh) * | 2015-12-31 | 2017-07-07 | 无锡华润安盛科技有限公司 | 高密度qfn封装体及其制备方法 |
JP6695156B2 (ja) * | 2016-02-02 | 2020-05-20 | エイブリック株式会社 | 樹脂封止型半導体装置 |
JP6607571B2 (ja) * | 2016-07-28 | 2019-11-20 | 株式会社東海理化電機製作所 | 半導体装置の製造方法 |
CN107195612A (zh) * | 2017-06-20 | 2017-09-22 | 南京矽邦半导体有限公司 | 一种基于加长半蚀刻拱形内引脚qfn框架及其封装芯片 |
JP7338204B2 (ja) * | 2019-04-01 | 2023-09-05 | 富士電機株式会社 | 半導体装置 |
JP7368055B2 (ja) * | 2019-06-21 | 2023-10-24 | ローム株式会社 | 半導体装置、および、半導体装置の実装構造 |
JP7304830B2 (ja) * | 2020-02-12 | 2023-07-07 | 三菱電機株式会社 | トランスファーモールド型パワーモジュール、リードフレーム、およびトランスファーモールド型パワーモジュールの製造方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030006055A1 (en) | 2001-07-05 | 2003-01-09 | Walsin Advanced Electronics Ltd | Semiconductor package for fixed surface mounting |
JP2003174136A (ja) * | 2001-12-07 | 2003-06-20 | Aoi Electronics Co Ltd | 樹脂モールド半導体装置 |
JP3606837B2 (ja) * | 2001-12-19 | 2005-01-05 | 株式会社三井ハイテック | リードフレームおよびこれを用いた半導体装置 |
JP2004022725A (ja) * | 2002-06-14 | 2004-01-22 | Renesas Technology Corp | 半導体装置 |
JP4111499B2 (ja) * | 2002-12-26 | 2008-07-02 | 株式会社三井ハイテック | リードフレーム |
JP4417150B2 (ja) * | 2004-03-23 | 2010-02-17 | 株式会社ルネサステクノロジ | 半導体装置 |
US7375416B2 (en) * | 2005-09-20 | 2008-05-20 | United Test And Assembly Center Ltd. | Leadframe enhancement and method of producing a multi-row semiconductor package |
JP2008198718A (ja) * | 2007-02-09 | 2008-08-28 | Asmo Co Ltd | 樹脂封止型半導体装置 |
JP5155644B2 (ja) * | 2007-07-19 | 2013-03-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20090032917A1 (en) * | 2007-08-02 | 2009-02-05 | M/A-Com, Inc. | Lead frame package apparatus and method |
JP2009076658A (ja) * | 2007-09-20 | 2009-04-09 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2010177272A (ja) | 2009-01-27 | 2010-08-12 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP5544583B2 (ja) * | 2009-10-16 | 2014-07-09 | アピックヤマダ株式会社 | リードフレーム、電子部品用基板及び電子部品 |
US8802500B2 (en) * | 2009-11-11 | 2014-08-12 | Stats Chippac Ltd. | Integrated circuit packaging system with leads and method of manufacture thereof |
TWM393039U (en) * | 2010-04-29 | 2010-11-21 | Kun Yuan Technology Co Ltd | Wire holder capable of reinforcing sealing connection and packaging structure thereof |
TWI489607B (zh) * | 2010-11-23 | 2015-06-21 | 登豐微電子股份有限公司 | 封裝結構 |
JP5798021B2 (ja) * | 2011-12-01 | 2015-10-21 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2011
- 2011-12-01 JP JP2011263744A patent/JP5798021B2/ja not_active Expired - Fee Related
-
2012
- 2012-09-27 TW TW101135676A patent/TWI540691B/zh not_active IP Right Cessation
- 2012-11-12 CN CN201210470646.7A patent/CN103137592B/zh active Active
- 2012-11-12 CN CN2012206136162U patent/CN202996818U/zh not_active Expired - Fee Related
- 2012-11-27 KR KR1020120134989A patent/KR101953393B1/ko active IP Right Grant
- 2012-12-03 US US13/692,286 patent/US8836106B2/en active Active
-
2014
- 2014-08-21 US US14/465,379 patent/US9443794B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN103137592B (zh) | 2017-09-05 |
TW201324696A (zh) | 2013-06-16 |
TWI540691B (zh) | 2016-07-01 |
US20130140714A1 (en) | 2013-06-06 |
KR20130061632A (ko) | 2013-06-11 |
JP2013118215A (ja) | 2013-06-13 |
CN202996818U (zh) | 2013-06-12 |
CN103137592A (zh) | 2013-06-05 |
US8836106B2 (en) | 2014-09-16 |
KR101953393B1 (ko) | 2019-02-28 |
US20140361422A1 (en) | 2014-12-11 |
US9443794B2 (en) | 2016-09-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5798021B2 (ja) | 半導体装置 | |
JP5618873B2 (ja) | 半導体装置の製造方法 | |
JP2009076658A (ja) | 半導体装置及びその製造方法 | |
JP2014220439A (ja) | 半導体装置の製造方法および半導体装置 | |
JP6357371B2 (ja) | リードフレーム、半導体装置及びリードフレームの製造方法 | |
TW200805526A (en) | Semiconductor device, and method of manufacturing the same | |
JP2009194059A (ja) | 半導体装置及びその製造方法 | |
JP2006100636A (ja) | 半導体装置の製造方法 | |
JP6164895B2 (ja) | 半導体装置の製造方法 | |
JP5585352B2 (ja) | リードフレーム、半導体装置及びその製造方法 | |
US20110062569A1 (en) | Semiconductor device package with down-set leads | |
JP2015060876A (ja) | 半導体装置の製造方法 | |
JP4566266B2 (ja) | 半導体装置の製造方法 | |
JP5512784B2 (ja) | 半導体装置の製造方法 | |
JP2011054626A (ja) | 半導体装置およびその製造方法 | |
JP5184558B2 (ja) | 半導体装置 | |
JP4651218B2 (ja) | 半導体装置の製造方法 | |
JP4835449B2 (ja) | 半導体装置 | |
JP2009231322A (ja) | 半導体装置の製造方法 | |
KR100384335B1 (ko) | 반도체패키지와 그 제조방법 | |
JP5824120B2 (ja) | 半導体装置 | |
JP2014112714A (ja) | 半導体装置 | |
JP2010050491A (ja) | 半導体装置の製造方法 | |
JP4535513B2 (ja) | 半導体装置 | |
JP2010177692A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140813 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150518 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150526 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150724 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150818 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150820 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5798021 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |