CN109564879A - 半导体装置的制造方法 - Google Patents
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Abstract
半导体装置的制造方法如下制造半导体装置(1):准备排列形成有多个电路图案形成区域(20)的引线框(2),在电路图案形成区域(20)安装电子部件而形成电子电路部(3),以覆盖电子电路部(3)并且供多个外引线露出的方式通过密封树脂形成第一密封体(4),切断连结多个外引线的拉杆(23)的一部分而在各个外引线形成锚定部,并且切断与引线框(2)连结的其他拉杆(22)和多个外引线而形成一次成型体(5),以覆盖一次成型体(5)的第一密封体(4)和锚定部的方式通过密封树脂形成第二密封体(6)而形成二次成型体。
Description
技术领域
本发明涉及半导体装置的制造方法。
背景技术
公知有一种半导体装置,具备内置有半导体芯片的模制部、和与半导体芯片一同内置于模制部且其一部分从模制部的一个面露出的引线端子(例如,参照专利文献1。)。
该半导体装置的从模制部露出的引线端子成为与连接器等连接的连接端子。该连接端子的锚定部形成于模制部内。该锚定部在被向连接端子延伸的方向拉伸时,以不从模制部脱落的方式,在与被拉伸的方向交叉的方向上形成宽幅。
专利文献1:日本特开2015-95486号
发明内容
本发明的目的在于提供半导体装置的制造方法,能够利用支承外引线的拉杆生成锚定部,而抑制制造成本。
本发明的一个实施方式的半导体装置的制造方法如下制造半导体装置:准备排列形成有多个电路图案形成区域的引线框,在电路图案形成区域安装电子部件而形成电子电路部,以覆盖电子电路部并且供多个外引线露出的方式通过密封树脂形成第1密封体,切断连结多个外引线的拉杆的一部分并在各个外引线形成锚定部,并且切断与引线框连结的其他拉杆和多个外引线并形成一次成型体,以覆盖一次成型体的第1密封体和锚定部的方式通过密封树脂形成第2密封体而形成二次成型体。
根据本发明的一个实施方式,能够提供半导体装置的制造方法,利用支承外引线的拉杆生成锚定部,而抑制制造成本。
附图说明
图1A是示出实施方式所涉及的半导体装置的俯视图。
图1B是示出半导体装置的一次成型体的一个例子的俯视图。
图2是示出实施方式所涉及的半导体装置的形成电路图案的引线框的俯视图。
图3A是示出实施方式所涉及的半导体装置的制造方法的俯视图。
图3B是示出实施方式所涉及的半导体装置的制造方法的俯视图。
图3C是示出实施方式所涉及的半导体装置的制造方法的俯视图。
图3D是示出实施方式所涉及的半导体装置的制造方法的俯视图。
图4A是示出变形例所涉及的半导体装置的锚定部的俯视图。
图4B是示出变形例所涉及的半导体装置的锚定部的俯视图。
图4C是示出变形例所涉及的半导体装置的锚定部的俯视图。
具体实施方式
(实施方式的摘要)
实施方式所涉及的半导体装置的制造方法如下:准备排列形成有多个电路图案形成区域的引线框,在电路图案形成区域安装电子部件而形成电子电路部,以覆盖电子电路部并且供多个外引线露出的方式通过密封树脂形成第1密封体,切断连结多个外引线的拉杆的一部分并在各个外引线形成锚定部,并且切断与引线框连结的其他拉杆和多个外引线并形成一次成型体,以覆盖一次成型体的第1密封体和锚定部的方式通过密封树脂形成第2密封体而形成二次成型体。
该半导体装置的制造方法在从引线框切下一次成型体时也形成锚定部,因此与不采用该方法的情况相比,利用支承外引线的拉杆生成锚定部,因而能够抑制制造成本。
[实施方式]
(半导体装置1的概要)
图1A是示出实施方式所涉及的半导体装置的俯视图,图1B是示出半导体装置的一次成型体的俯视图。图2是示出实施方式所涉及的半导体装置的形成电路图案的引线框的俯视图。此外,在以下记载的实施方式所涉及的各图中,存在图形间的比例与实际的比例不同的情况。
作为一个例子,如图1A和图1B所示,本实施方式的半导体装置1为具备包括磁检测IC(集成电路)30在内的电子电路部3的磁传感器装置。此外,半导体装置1并不限定于磁传感器装置,可以是检测压力的压力传感器装置、测定温度的温度传感器装置等,也可以是具备发光元件等的照明装置等。
作为一个例子,该半导体装置1构成为配置于车辆,对检测对象的接近进行检测。此外,作为一个例子,检测对象为制动踏板、安全带装置的舌形板等。
如图1A和图1B所示,该半导体装置1通过对具备对电子电路部3进行密封而形成的第1密封体4的一次成型体5进一步进行密封而形成。即、半导体装置1通过两次的模制成型而被形成。
(一次成型体5的结构)
例如,如图2所示,一次成型体5形成于引线框2的每个电路图案形成区域20。例如,该引线框2为铝、铜、铁等金属材料或合金材料的薄板。
如图2所示,在该引线框2形成有多个电路图案形成区域20。该电路图案形成区域20形成有与形成的一次成型体5的电子电路部3对应的电路图案21。
该电路图案21成为供电子电路部3的配线、电子部件配置的垫板。而且,电路图案21通过冲切(冲压)、蚀刻等形成。
另外,电路图案21通过拉杆22、拉杆23、外引线25b~外引线28b的端部与包围电路图案形成区域20的框架200相连结的方式被形成。
如图2所示,该拉杆22将内引线25a~内引线28a与框架200连结。即、内引线25a~内引线28a被多个拉杆22支承于框架200。
如图2所示,拉杆23与排列成一列的外引线25b~外引线28b交叉并与框架200的两侧连结。即、外引线25b~外引线28b被拉杆23支承于框架200。
另外,外引线25b~外引线28b的端部形成为越靠近前端变得越细,且该前端与从框架200突出的部分连结。该突出的部分与前端一样变细,因此与外引线连结的部分的宽度最窄而变得容易切断。
此处,内引线25a和外引线25b为加工引线框2而形成的一根引线。该内引线25a被第1密封体4密封。另外,外引线25b从第1密封体4露出。相同地,内引线26a~内引线28a和外引线26b~外引线28b分别为一根引线。此外,引线的数量与所形成的电子电路部3对应地变更。
电子电路部3通过在该内引线25a~内引线28a上接合电子部件而形成。如图1B所示,本实施方式的电子电路部3作为电子部件,具有磁检测IC30、2个齐纳二极管31、和2个电容器32。
作为一个例子,磁检测IC30使用银膏等粘合剂配置于内引线25a。而且,磁检测IC30通过线材接合法与内引线25a~内引线28a电连接。
例如,该磁检测IC30具备:磁检测元件、放大磁检测元件的输出的放大器、和根据被放大的输出判定检测对象的接近的控制部等。例如,磁检测元件由对检测对象生成的磁场的强度进行检测的霍尔元件、和对磁场的方向的变化进行检测的磁阻元件等构成。
例如,2个齐纳二极管31与内引线25a和内引线26a之间电连接,与内引线27a和内引线28a之间电连接。相同地,例如,2个电容器32与内引线25a和内引线26a之间电连接,与内引线27a和内引线28a之间电连接。该齐纳二极管31和电容器32构成为保护磁检测IC30免于静电、噪声等影响的保护电路。例如,齐纳二极管31以将施加于磁检测IC30的电压保持为恒定的方式被连接。另外,例如,电容器32以除去从齐纳二极管31产生的噪声的方式被连接。
如图1B所示,在外引线25b~外引线28b形成有锚定部25c~锚定部28c。锚定部25c~锚定部28c通过切断图2所示的拉杆23的一部分而形成。因此,锚定部25c具有以与外引线25b的长度方向交叉的方式突出的形状。相同地,其他的锚定部26c~锚定部28c具有以与外引线26b~外引线28b的长度方向交叉的方式突出的形状。
如图1A所示,该锚定部25c~锚定部28c被第2密封体6密封。锚定部25c~锚定部28c用于在将外引线25b~外引线28b使用为连接端子29的情况下,使外引线25b~外引线28b不会因连接器的拔插而从第2密封体6脱落。
例如,第1密封体4通过使用了密封树脂的模制成型而形成。该密封树脂是以环氧树脂为主要成分并添加了二氧化硅填充材料等而成的热固化性成型材料。例如,第1密封体4形成为保护电子电路部3免于光、热以及湿度等影响。
(第2密封体6的结构)
第2密封体6以使一次成型体5的外引线25b~外引线28b的一部分露出的方式进行密封而形成。作为一个例子,第2密封体6使用PE(聚乙烯)、PP(聚丙烯)等热塑性树脂而形成。
第2密封体6成为半导体装置1的外装,具有与安装场所对应的形状。而且,第2密封体6形成有能够供连接对象的连接器插入的连接器部50。该连接器部50具有凹部形状,在该凹部内插入连接对象的连接器。
而且,外引线25b~外引线28b作为连接端子29向形成于第2密封体6的连接器部50内露出。换而言之,在连接器部50的内部,外引线25b~外引线28b的端部露出,而形成连接端子29。
以下,参照图3A~图3D的附图,对本实施方式的半导体装置1的制造方法的一个例子进行说明。
(半导体装置1的制造方法)
图3A~图3D是用于对实施方式所涉及的半导体装置的制造方法进行说明的俯视图。图3A~图3D图示了一个电路图案形成区域20。
半导体装置1的制造方法如下:准备排列形成有多个电路图案形成区域20的引线框2,在电路图案形成区域20安装电子部件而形成电子电路部3,以覆盖电子电路部3并且供多个外引线(外引线25b~外引线28b)露出的方式通过密封树脂形成第1密封体4,切断连结多个外引线的拉杆23的一部分并在各个外引线形成锚定部25c~锚定部28c,并且切断与引线框2连结的其他拉杆22和多个外引线并形成一次成型体5,以覆盖一次成型体5的第1密封体4和锚定部25c~锚定部28c的方式通过密封树脂形成第2密封体6而形成二次成型体。
具体而言,如图3A所示,首先准备排列形成有多个电路图案形成区域20的引线框2。
接着,如图3B所示,在电路图案形成区域20安装电子部件而形成电子电路部3。作为一个例子,该电子部件为磁检测IC30、齐纳二极管31、以及电容器32。
接着,如图3C所示,以覆盖电子电路部3并且多个外引线(外引线25b~外引线28b)露出的方式通过密封树脂形成第1密封体4。该密封在拉杆22和拉杆33连结于引线框2的框架200的状态下进行。
接着,如图3D所示,切断连结外引线25b~外引线28b的拉杆23的一部分而在各个外引线形成锚定部25c~锚定部28c,并且切断与引线框2连结的其他拉杆22和外引线25b~外引线28b而形成一次成型体5。
用于形成锚定部25c~锚定部28c的拉杆23的切断的宽度W优选在能够保持彼此的绝缘性的范围内缩小。这是因为,锚定部从外引线突出的突出量越多,防脱性越高。作为一个例子,切断的宽度W为外引线的宽度左右。
接着,以覆盖一次成型体5的第1密封体4和锚定部25c~锚定部28c的方式通过密封树脂形成第2密封体6而形成二次成型体,获得图1A所示的半导体装置1。
(变形例)
图4A~图4C是示出变形例所涉及的半导体装置的锚定部的俯视图。在该图4A~图4C中图示了外引线的一部分。
此外,作为变形例,锚定部也可以在一个外引线形成多个。即、也可以形成多个将外引线25b~外引线28b连结的拉杆23,在每个外引线形成多个锚定部。在该变形例中,与锚定部为一个的情况相比,能够更加抑制从第1密封体4的脱落。
图4A示出了在外引线25b形成锚定部25c和锚定部25d,在外引线26b形成锚定部26c和锚定部26d的一个例子。此外,第1密封体4侧的锚定部25c和锚定部26c也可以比锚定部25d和锚定部26d突出量多。
另外,作为其他变形例,锚定部并不限定于矩形状,例如,也可以形成为外引线侧的宽度大于锚定部的前端侧的宽度。在该变形例中,与不采用该结构的情况相比,能够容易切断并且抑制从第1密封体4的脱落。图4B示出了外引线侧的宽度大于锚定部的前端侧的宽度的锚定部25c和锚定部26c的一个例子。
作为又一其他变形例,锚定部也可以具有向外引线的前端侧弯折的形状。在该变形例中,与不采用该结构的情况相比,能够更加抑制从第1密封体4的脱落。图4C示出了外引线25b的锚定部25c具有向前端方向弯曲的弯曲部250c,并且外引线26b的锚定部26c具有向前端方向弯曲的弯曲部260c的一个例子。
(实施方式的效果)
本实施方式所涉及的半导体装置1的制造方法能够利用支承外引线25b~外引线28b的拉杆23生成锚定部25c~锚定部28c,而抑制制造成本。具体而言,半导体装置1的制造方法在从引线框2切下一次成型体5时切断拉杆23的一部分从而形成锚定部25c~锚定部28c。因此,半导体装置1的制造方法将本来因切断而消失的拉杆23仅切断其一部分而留下,由此生成锚定部25c~锚定部28c,因此与不采用该方法的情况相比,能够抑制制造成本。
半导体装置1具有被二次成型体密封的锚定部25c~锚定部28c,因此与没有锚定部的情况相比,能够抑制外引线25b~外引线28b从第1密封体4的脱落,提高连接端子29的可靠性。
以上,对本发明的几个实施方式和变形例进行了说明,但这些实施方式和变形例只不过是一个例子,并不限定权利要求书所涉及的发明。这些新的实施方式和变形例能够以其他各种方式实施,在不脱离本发明的主旨的范围内,能够进行各种省略、置换、以及变更等。另外,在这些实施方式和变形例中说明的特征的组合的全部并不一定是用于解决发明的课题的手段所必须的。另外,这些实施方式和变形例包含于发明的范围和主旨内,并且也包含于权利要求书所记载的发明及与其等同的范围内。
附图标记的说明
1…半导体装置;2…引线框;3…电子电路部;4…第1密封体;5…一次成型体;6…第2密封体;20…电路图案形成区域;23…拉杆;25b~28b…外引线;25c~28c…锚定部;25d、26d…锚定部;29…连接端子;50…连接器部。
Claims (6)
1.一种半导体装置的制造方法,其特征在于,
准备排列形成有多个电路图案形成区域的引线框,
在所述电路图案形成区域安装电子部件而形成电子电路部,
以覆盖所述电子电路部并且多个外引线露出的方式通过密封树脂形成第1密封体,
切断连结所述多个外引线的拉杆的一部分而在各个所述外引线形成锚定部,并且切断与所述引线框连结的其他拉杆和所述多个外引线而形成一次成型体,
以覆盖所述一次成型体的所述第1密封体和所述锚定部的方式通过密封树脂形成第2密封体而形成二次成型体。
2.根据权利要求1所述的半导体装置的制造方法,其特征在于,
所述外引线作为连接端子向形成于所述第2密封体的连接器部内露出。
3.根据权利要求1或2所述的半导体装置的制造方法,其特征在于,
形成多个将所述多个外引线连结的拉杆,在每个所述外引线形成多个锚定部。
4.根据权利要求1或3所述的半导体装置的制造方法,其特征在于,
将所述多个外引线连结的拉杆的一部分的切断的宽度等于所述外引线的宽度。
5.根据权利要求1、3或4所述的半导体装置的制造方法,其特征在于,
所述锚定部的前端部的宽度窄于所述外引线侧的宽度。
6.根据权利要求1、3或4所述的半导体装置的制造方法,其特征在于,
所述锚定部具有弯曲部。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000150765A (ja) * | 1998-10-21 | 2000-05-30 | Amkor Technology Inc | 半導体集積回路プラスチックパッケ―ジ、およびそのパッケ―ジの製造のための超小型リ―ドフレ―ムおよび製造方法 |
CN1499622A (zh) * | 2002-11-01 | 2004-05-26 | ���µ�����ҵ��ʽ���� | 引线框及制造方法以及树脂密封型半导体器件及制造方法 |
JP2006261242A (ja) * | 2005-03-15 | 2006-09-28 | Toshiba Corp | リードフレームおよびそれを用いた光半導体装置 |
JP2013118215A (ja) * | 2011-12-01 | 2013-06-13 | Renesas Electronics Corp | 半導体装置 |
JP2014017390A (ja) * | 2012-07-10 | 2014-01-30 | Apic Yamada Corp | リードフレーム、プリモールドリードフレーム、半導体装置、プリモールドリードフレームの製造方法、および、半導体装置の製造方法 |
CN104221145A (zh) * | 2012-03-23 | 2014-12-17 | 德克萨斯仪器股份有限公司 | 具有配置为模块的多级引线框的封装半导体器件 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04364766A (ja) * | 1991-06-12 | 1992-12-17 | Yamada Seisakusho Co Ltd | 半導体装置の製造方法および半導体装置 |
JPH08116009A (ja) * | 1994-10-18 | 1996-05-07 | Hitachi Ltd | 半導体装置の製造方法 |
JP2004063688A (ja) * | 2002-07-26 | 2004-02-26 | Mitsubishi Electric Corp | 半導体装置及び半導体アセンブリモジュール |
JP5467799B2 (ja) * | 2009-05-14 | 2014-04-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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US8530981B2 (en) * | 2009-12-31 | 2013-09-10 | Texas Instruments Incorporated | Leadframe-based premolded package having acoustic air channel for micro-electro-mechanical system |
WO2015030637A1 (en) * | 2013-08-26 | 2015-03-05 | Telefonaktiebolaget L M Ericsson (Publ) | Apparatus and method for processing data streams in a communication network |
JP2015095486A (ja) | 2013-11-08 | 2015-05-18 | アイシン精機株式会社 | 半導体装置 |
US9666511B2 (en) * | 2015-01-15 | 2017-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Isolation method for a stand alone high voltage laterally-diffused metal-oxide semiconductor (LDMOS) transistor |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000150765A (ja) * | 1998-10-21 | 2000-05-30 | Amkor Technology Inc | 半導体集積回路プラスチックパッケ―ジ、およびそのパッケ―ジの製造のための超小型リ―ドフレ―ムおよび製造方法 |
CN1499622A (zh) * | 2002-11-01 | 2004-05-26 | ���µ�����ҵ��ʽ���� | 引线框及制造方法以及树脂密封型半导体器件及制造方法 |
JP2006261242A (ja) * | 2005-03-15 | 2006-09-28 | Toshiba Corp | リードフレームおよびそれを用いた光半導体装置 |
JP2013118215A (ja) * | 2011-12-01 | 2013-06-13 | Renesas Electronics Corp | 半導体装置 |
CN104221145A (zh) * | 2012-03-23 | 2014-12-17 | 德克萨斯仪器股份有限公司 | 具有配置为模块的多级引线框的封装半导体器件 |
JP2014017390A (ja) * | 2012-07-10 | 2014-01-30 | Apic Yamada Corp | リードフレーム、プリモールドリードフレーム、半導体装置、プリモールドリードフレームの製造方法、および、半導体装置の製造方法 |
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